Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clkmgr_byp.u_en_sync	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req	100.00	100.00					100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_lc_byp_req

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1610	1610	0	0
OutputsKnown_A	336554122	332203220	0	0
gen_flops.OutputDelay_A	336554122	332189206	0	4830

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610	1610	0	0
T5	2	2	0	0
T6	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0
T28	2	2	0	0
T29	2	2	0	0
T30	2	2	0	0
T31	2	2	0	0
T32	2	2	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336554122	332203220	0	0
T5	364210	363828	0	0
T6	20642	20598	0	0
T8	3724	3334	0	0
T9	4668	4576	0	0
T10	3756	3668	0	0
T28	2152	2128	0	0
T29	2676	2484	0	0
T30	7240	6760	0	0
T31	2578	2472	0	0
T32	1742	1696	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336554122	332189206	0	4830
T5	364210	363822	0	6
T6	20642	20592	0	6
T8	3724	3328	0	6
T9	4668	4570	0	6
T10	3756	3662	0	6
T28	2152	2122	0	6
T29	2676	2478	0	6
T30	7240	6754	0	6
T31	2578	2466	0	6
T32	1742	1690	0	6

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	168277061	166101610	0	0
gen_flops.OutputDelay_A	168277061	166094603	0	2415

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	166101610	0	0
T5	182105	181914	0	0
T6	10321	10299	0	0
T8	1862	1667	0	0
T9	2334	2288	0	0
T10	1878	1834	0	0
T28	1076	1064	0	0
T29	1338	1242	0	0
T30	3620	3380	0	0
T31	1289	1236	0	0
T32	871	848	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	166094603	0	2415
T5	182105	181911	0	3
T6	10321	10296	0	3
T8	1862	1664	0	3
T9	2334	2285	0	3
T10	1878	1831	0	3
T28	1076	1061	0	3
T29	1338	1239	0	3
T30	3620	3377	0	3
T31	1289	1233	0	3
T32	871	845	0	3

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	168277061	166101610	0	0
gen_flops.OutputDelay_A	168277061	166094603	0	2415

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	166101610	0	0
T5	182105	181914	0	0
T6	10321	10299	0	0
T8	1862	1667	0	0
T9	2334	2288	0	0
T10	1878	1834	0	0
T28	1076	1064	0	0
T29	1338	1242	0	0
T30	3620	3380	0	0
T31	1289	1236	0	0
T32	871	848	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	166094603	0	2415
T5	182105	181911	0	3
T6	10321	10296	0	3
T8	1862	1664	0	3
T9	2334	2285	0	3
T10	1878	1831	0	3
T28	1076	1061	0	3
T29	1338	1239	0	3
T30	3620	3377	0	3
T31	1289	1233	0	3
T32	871	845	0	3