Module Definition
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Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Module : prim_subreg_shadow
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T65,T66
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T65,T66
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T65,T66
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT64,T65,T66
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT64,T65,T66

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T65,T66

Branch Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Module : prim_subreg_shadow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 10100 10100 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10100 10100 0 0
T5 10 10 0 0
T6 10 10 0 0
T8 10 10 0 0
T9 10 10 0 0
T10 10 10 0 0
T28 10 10 0 0
T29 10 10 0 0
T30 10 10 0 0
T31 10 10 0 0
T32 10 10 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T5 1186308 1185200 0 0
T6 407622 406838 0 0
T8 11766 10636 0 0
T9 57084 56174 0 0
T10 22408 21940 0 0
T28 113394 112310 0 0
T29 8588 8010 0 0
T30 23172 21794 0 0
T31 32880 31684 0 0
T32 21422 20860 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T67,T68
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T66,T69
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T67,T68
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT64,T66,T69
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT64,T66,T69

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T66,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 491904571 487682074 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491904571 487682074 0 0
T5 180217 180027 0 0
T6 61931 61797 0 0
T8 1805 1616 0 0
T9 8297 8134 0 0
T10 3340 3260 0 0
T28 17224 17035 0 0
T29 1310 1216 0 0
T30 3476 3245 0 0
T31 4952 4749 0 0
T32 3309 3215 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T66,T67
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T66,T69
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T66,T67
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT66,T69,T67
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT66,T69,T67

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T66,T69

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 491904571 487682074 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 491904571 487682074 0 0
T5 180217 180027 0 0
T6 61931 61797 0 0
T8 1805 1616 0 0
T9 8297 8134 0 0
T10 3340 3260 0 0
T28 17224 17035 0 0
T29 1310 1216 0 0
T30 3476 3245 0 0
T31 4952 4749 0 0
T32 3309 3215 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T66,T67
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T65,T66
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T66,T67
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT64,T66,T69
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT64,T66,T69

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T65,T66

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 245172764 244127585 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245172764 244127585 0 0
T5 90062 90014 0 0
T6 30933 30899 0 0
T8 863 808 0 0
T9 4970 4942 0 0
T10 1811 1790 0 0
T28 8613 8572 0 0
T29 643 608 0 0
T30 1836 1767 0 0
T31 2569 2514 0 0
T32 1635 1607 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T67,T68
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T65,T66
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T67,T68
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT69,T70,T71
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT69,T70,T71

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T65,T66

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 245172764 244127585 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245172764 244127585 0 0
T5 90062 90014 0 0
T6 30933 30899 0 0
T8 863 808 0 0
T9 4970 4942 0 0
T10 1811 1790 0 0
T28 8613 8572 0 0
T29 643 608 0 0
T30 1836 1767 0 0
T31 2569 2514 0 0
T32 1635 1607 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T65,T66
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T65,T66
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T65,T66
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT64,T65,T66
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT64,T65,T66

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T65,T66

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 122585755 122063270 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122585755 122063270 0 0
T5 45031 45007 0 0
T6 15466 15449 0 0
T8 432 404 0 0
T9 2483 2469 0 0
T10 904 894 0 0
T28 4306 4285 0 0
T29 321 304 0 0
T30 917 883 0 0
T31 1284 1256 0 0
T32 818 804 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T66,T72
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T65,T66
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T66,T72
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT64,T65,T66
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT64,T65,T66

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T65,T66

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 122585755 122063270 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122585755 122063270 0 0
T5 45031 45007 0 0
T6 15466 15449 0 0
T8 432 404 0 0
T9 2483 2469 0 0
T10 904 894 0 0
T28 4306 4285 0 0
T29 321 304 0 0
T30 917 883 0 0
T31 1284 1256 0 0
T32 818 804 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T66,T67
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T65,T66
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T66,T67
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT64,T66,T67
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT64,T66,T67

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T65,T66

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 525408335 520925934 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525408335 520925934 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T66,T67
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T66,T72
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T66,T67
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT64,T66,T67
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT64,T66,T67

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T66,T72

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 525408335 520925934 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525408335 520925934 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T66,T73
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T65,T66
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T66,T73
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT64,T65,T66
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT64,T65,T66

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T65,T66

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 252237709 250094595 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 252237709 250094595 0 0
T5 90112 90017 0 0
T6 30967 30900 0 0
T8 902 807 0 0
T9 4149 4068 0 0
T10 1670 1630 0 0
T28 8612 8518 0 0
T29 655 609 0 0
T30 1737 1622 0 0
T31 2476 2375 0 0
T32 1564 1517 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT64,T66,T67
11CoveredT5,T6,T7

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT8,T9,T10
01CoveredT64,T65,T66
10CoveredT4,T1,T20

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101CoveredT5,T6,T7
110CoveredT64,T66,T67
111CoveredT5,T6,T7

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT8,T9,T10
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011CoveredT5,T6,T7
1101CoveredT66,T67,T68
1110Not Covered
1111CoveredT5,T6,T7

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T6,T7
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT8,T9,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT5,T6,T7
11CoveredT66,T67,T68

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT64,T65,T66

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T5,T6,T7


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T8,T9,T10
0 1 - Covered T5,T6,T7
0 0 1 Covered T4,T1,T20
0 0 0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 252237709 250094595 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 252237709 250094595 0 0
T5 90112 90017 0 0
T6 30967 30900 0 0
T8 902 807 0 0
T9 4149 4068 0 0
T10 1670 1630 0 0
T28 8612 8518 0 0
T29 655 609 0 0
T30 1737 1622 0 0
T31 2476 2375 0 0
T32 1564 1517 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%