Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	168277061	23990642	0	59

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	23990642	0	59
T1	0	71916	0	0
T2	0	12511	0	1
T3	0	34512	0	1
T4	74190	0	0	0
T5	182105	1199	0	1
T6	10321	867	0	1
T7	4261	0	0	0
T13	0	41948	0	0
T14	0	26506	0	0
T15	0	15334	0	1
T16	0	406526	0	0
T17	0	37169	0	0
T31	1289	0	0	0
T32	871	0	0	0
T36	2673	0	0	0
T37	13669	0	0	0
T38	61434	0	0	0
T39	0	0	0	1
T40	2152	0	0	0
T124	0	0	0	1
T125	0	0	0	1
T126	0	0	0	1
T127	0	0	0	1