Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	169255509	5338035	0	0
clk_enables_rd_A	169255509	57069	0	0
clk_hints_rd_A	169255509	50978	0	0
extclk_ctrl_rd_A	169255509	64079	0	0
extclk_ctrl_regwen_rd_A	169255509	49294	0	0
jitter_enable_rd_A	169255509	71946	0	0
jitter_regwen_rd_A	169255509	56081	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169255509	5338035	0	0
T1	406249	205008	0	0
T2	52357	0	0	0
T14	0	43077	0	0
T16	0	48931	0	0
T18	0	61526	0	0
T19	0	136856	0	0
T20	127047	0	0	0
T21	1317	0	0	0
T22	888	0	0	0
T23	2455	0	0	0
T24	2293	0	0	0
T25	63609	0	0	0
T26	1502	0	0	0
T27	62866	0	0	0
T33	0	130056	0	0
T35	0	116332	0	0
T74	0	141090	0	0
T75	0	117346	0	0
T76	0	161590	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169255509	57069	0	0
T3	119171	0	0	0
T13	144730	0	0	0
T16	0	1911	0	0
T18	0	2432	0	0
T27	62866	10	0	0
T35	0	4660	0	0
T48	1135	0	0	0
T74	0	3141	0	0
T79	0	5	0	0
T93	0	2	0	0
T108	2493	0	0	0
T111	1093	0	0	0
T119	2460	0	0	0
T120	2029	0	0	0
T143	0	1	0	0
T144	0	2605	0	0
T145	0	3	0	0
T146	10444	0	0	0
T147	1830	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169255509	50978	0	0
T3	119171	0	0	0
T13	144730	0	0	0
T16	0	1740	0	0
T18	0	2140	0	0
T27	62866	7	0	0
T35	0	3875	0	0
T48	1135	0	0	0
T74	0	2905	0	0
T79	0	1	0	0
T93	0	3	0	0
T108	2493	0	0	0
T111	1093	0	0	0
T119	2460	0	0	0
T120	2029	0	0	0
T143	0	2	0	0
T144	0	2296	0	0
T146	10444	0	0	0
T147	1830	0	0	0
T148	0	2655	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169255509	64079	0	0
T5	182105	0	0	0
T6	10321	0	0	0
T9	2334	67	0	0
T10	1878	0	0	0
T13	0	91	0	0
T23	0	50	0	0
T27	0	26	0	0
T28	1076	0	0	0
T29	1338	0	0	0
T30	3620	0	0	0
T31	1289	0	0	0
T32	871	0	0	0
T36	2673	0	0	0
T92	0	48	0	0
T108	0	59	0	0
T111	0	18	0	0
T119	0	64	0	0
T149	0	42	0	0
T150	0	23	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169255509	49294	0	0
T16	168711	1917	0	0
T17	357166	0	0	0
T18	219499	2223	0	0
T19	398890	0	0	0
T33	257329	0	0	0
T35	0	3718	0	0
T39	11432	0	0	0
T74	0	2906	0	0
T107	51110	0	0	0
T144	0	2234	0	0
T148	0	2355	0	0
T151	0	17	0	0
T152	0	29	0	0
T153	0	2107	0	0
T154	0	34	0	0
T155	1818	0	0	0
T156	1392	0	0	0
T157	798	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169255509	71946	0	0
T3	119171	0	0	0
T13	144730	0	0	0
T16	0	2537	0	0
T18	0	2809	0	0
T27	62866	256	0	0
T35	0	5673	0	0
T48	1135	0	0	0
T74	0	4126	0	0
T79	0	128	0	0
T93	0	126	0	0
T108	2493	0	0	0
T111	1093	0	0	0
T119	2460	0	0	0
T120	2029	0	0	0
T143	0	115	0	0
T144	0	3135	0	0
T145	0	65	0	0
T146	10444	0	0	0
T147	1830	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169255509	56081	0	0
T16	168711	2050	0	0
T17	357166	0	0	0
T18	219499	2464	0	0
T19	398890	0	0	0
T33	257329	0	0	0
T35	0	4888	0	0
T39	11432	0	0	0
T44	0	4458	0	0
T74	0	2986	0	0
T107	51110	0	0	0
T144	0	2749	0	0
T148	0	2795	0	0
T153	0	2502	0	0
T155	1818	0	0	0
T156	1392	0	0	0
T157	798	0	0	0
T158	0	4134	0	0
T159	0	2306	0	0