Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT9,T10,T28
11CoveredT9,T10,T28

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 489171663 4712 0 0
g_div2.Div2Whole_A 489171663 5419 0 0
g_div4.Div4Stepped_A 243853041 4645 0 0
g_div4.Div4Whole_A 243853041 5222 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 489171663 4712 0 0
T1 0 64 0 0
T5 180217 0 0 0
T6 61932 0 0 0
T9 8297 14 0 0
T10 3341 4 0 0
T23 0 4 0 0
T26 0 1 0 0
T27 0 8 0 0
T28 17224 2 0 0
T29 1311 0 0 0
T30 3476 8 0 0
T31 4953 3 0 0
T32 3309 0 0 0
T36 2674 10 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 489171663 5419 0 0
T1 0 74 0 0
T5 180217 0 0 0
T6 61932 0 0 0
T9 8297 14 0 0
T10 3341 8 0 0
T23 0 8 0 0
T27 0 8 0 0
T28 17224 2 0 0
T29 1311 0 0 0
T30 3476 9 0 0
T31 4953 6 0 0
T32 3309 0 0 0
T36 2674 13 0 0
T119 0 8 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 243853041 4645 0 0
T1 0 63 0 0
T5 90062 0 0 0
T6 30933 0 0 0
T9 4970 14 0 0
T10 1811 4 0 0
T23 0 3 0 0
T26 0 1 0 0
T27 0 8 0 0
T28 8613 2 0 0
T29 643 0 0 0
T30 1837 8 0 0
T31 2569 3 0 0
T32 1636 0 0 0
T36 1485 10 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 243853041 5222 0 0
T1 0 73 0 0
T5 90062 0 0 0
T6 30933 0 0 0
T9 4970 14 0 0
T10 1811 7 0 0
T23 0 8 0 0
T27 0 8 0 0
T28 8613 2 0 0
T29 643 0 0 0
T30 1837 7 0 0
T31 2569 6 0 0
T32 1636 0 0 0
T36 1485 11 0 0
T119 0 7 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT9,T10,T28
11CoveredT9,T10,T28

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 489171663 4712 0 0
g_div2.Div2Whole_A 489171663 5419 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 489171663 4712 0 0
T1 0 64 0 0
T5 180217 0 0 0
T6 61932 0 0 0
T9 8297 14 0 0
T10 3341 4 0 0
T23 0 4 0 0
T26 0 1 0 0
T27 0 8 0 0
T28 17224 2 0 0
T29 1311 0 0 0
T30 3476 8 0 0
T31 4953 3 0 0
T32 3309 0 0 0
T36 2674 10 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 489171663 5419 0 0
T1 0 74 0 0
T5 180217 0 0 0
T6 61932 0 0 0
T9 8297 14 0 0
T10 3341 8 0 0
T23 0 8 0 0
T27 0 8 0 0
T28 17224 2 0 0
T29 1311 0 0 0
T30 3476 9 0 0
T31 4953 6 0 0
T32 3309 0 0 0
T36 2674 13 0 0
T119 0 8 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT9,T10,T28
11CoveredT9,T10,T28

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 243853041 4645 0 0
g_div4.Div4Whole_A 243853041 5222 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 243853041 4645 0 0
T1 0 63 0 0
T5 90062 0 0 0
T6 30933 0 0 0
T9 4970 14 0 0
T10 1811 4 0 0
T23 0 3 0 0
T26 0 1 0 0
T27 0 8 0 0
T28 8613 2 0 0
T29 643 0 0 0
T30 1837 8 0 0
T31 2569 3 0 0
T32 1636 0 0 0
T36 1485 10 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 243853041 5222 0 0
T1 0 73 0 0
T5 90062 0 0 0
T6 30933 0 0 0
T9 4970 14 0 0
T10 1811 7 0 0
T23 0 8 0 0
T27 0 8 0 0
T28 8613 2 0 0
T29 643 0 0 0
T30 1837 7 0 0
T31 2569 6 0 0
T32 1636 0 0 0
T36 1485 11 0 0
T119 0 7 0 0

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