Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	504831183	438	0	0
StatusRise_A	504831183	438	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504831183	438	0	0
T1	1218747	0	0	0
T2	157071	0	0	0
T4	222570	0	0	0
T7	12783	0	0	0
T32	2613	9	0	0
T36	8019	0	0	0
T37	41007	0	0	0
T38	184302	0	0	0
T40	6456	0	0	0
T47	2490	0	0	0
T48	0	12	0	0
T49	0	12	0	0
T55	0	9	0	0
T157	0	10	0	0
T160	0	2	0	0
T161	0	9	0	0
T162	0	10	0	0
T163	0	7	0	0
T164	0	3	0	0
T165	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504831183	438	0	0
T1	1218747	0	0	0
T2	157071	0	0	0
T4	222570	0	0	0
T7	12783	0	0	0
T32	2613	9	0	0
T36	8019	0	0	0
T37	41007	0	0	0
T38	184302	0	0	0
T40	6456	0	0	0
T47	2490	0	0	0
T48	0	12	0	0
T49	0	12	0	0
T55	0	9	0	0
T157	0	10	0	0
T160	0	2	0	0
T161	0	9	0	0
T162	0	10	0	0
T163	0	7	0	0
T164	0	3	0	0
T165	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	168277061	139	0	0
StatusRise_A	168277061	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	139	0	0
T1	406249	0	0	0
T2	52357	0	0	0
T4	74190	0	0	0
T7	4261	0	0	0
T32	871	3	0	0
T36	2673	0	0	0
T37	13669	0	0	0
T38	61434	0	0	0
T40	2152	0	0	0
T47	830	0	0	0
T48	0	5	0	0
T49	0	3	0	0
T55	0	3	0	0
T157	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	139	0	0
T1	406249	0	0	0
T2	52357	0	0	0
T4	74190	0	0	0
T7	4261	0	0	0
T32	871	3	0	0
T36	2673	0	0	0
T37	13669	0	0	0
T38	61434	0	0	0
T40	2152	0	0	0
T47	830	0	0	0
T48	0	5	0	0
T49	0	3	0	0
T55	0	3	0	0
T157	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	168277061	148	0	0
StatusRise_A	168277061	148	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	148	0	0
T1	406249	0	0	0
T2	52357	0	0	0
T4	74190	0	0	0
T7	4261	0	0	0
T32	871	2	0	0
T36	2673	0	0	0
T37	13669	0	0	0
T38	61434	0	0	0
T40	2152	0	0	0
T47	830	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0
T164	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	148	0	0
T1	406249	0	0	0
T2	52357	0	0	0
T4	74190	0	0	0
T7	4261	0	0	0
T32	871	2	0	0
T36	2673	0	0	0
T37	13669	0	0	0
T38	61434	0	0	0
T40	2152	0	0	0
T47	830	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0
T164	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	168277061	151	0	0
StatusRise_A	168277061	151	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	151	0	0
T1	406249	0	0	0
T2	52357	0	0	0
T4	74190	0	0	0
T7	4261	0	0	0
T32	871	4	0	0
T36	2673	0	0	0
T37	13669	0	0	0
T38	61434	0	0	0
T40	2152	0	0	0
T47	830	0	0	0
T48	0	4	0	0
T49	0	4	0	0
T55	0	4	0	0
T157	0	2	0	0
T161	0	3	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	151	0	0
T1	406249	0	0	0
T2	52357	0	0	0
T4	74190	0	0	0
T7	4261	0	0	0
T32	871	4	0	0
T36	2673	0	0	0
T37	13669	0	0	0
T38	61434	0	0	0
T40	2152	0	0	0
T47	830	0	0	0
T48	0	4	0	0
T49	0	4	0	0
T55	0	4	0	0
T157	0	2	0	0
T161	0	3	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0