Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	52639	0	0
CgEnOn_A	2147483647	43518	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52639	0	0
T1	4130932	0	0	0
T2	481147	0	0	0
T4	595374	0	0	0
T5	405422	3	0	0
T6	139297	3	0	0
T7	134196	0	0	0
T8	4002	29	0	0
T9	19899	3	0	0
T10	7725	3	0	0
T19	0	5	0	0
T28	38755	3	0	0
T29	2929	34	0	0
T30	7966	13	0	0
T31	11281	3	0	0
T32	36598	22	0	0
T36	24424	0	0	0
T37	415267	0	0	0
T38	468804	0	0	0
T40	80711	8	0	0
T47	34069	1	0	0
T48	0	20	0	0
T49	0	25	0	0
T55	0	10	0	0
T157	0	25	0	0
T160	0	5	0	0
T161	0	15	0	0
T162	0	15	0	0
T163	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43518	0	0
T1	4130932	641	0	0
T2	481147	0	0	0
T4	595374	0	0	0
T5	405422	0	0	0
T6	139297	0	0	0
T7	134196	0	0	0
T8	4002	26	0	0
T9	19899	0	0	0
T10	7725	0	0	0
T14	0	162	0	0
T19	0	4	0	0
T21	0	47	0	0
T24	0	4	0	0
T27	0	58	0	0
T28	38755	0	0	0
T29	2929	31	0	0
T30	7966	10	0	0
T31	11281	0	0	0
T32	36598	19	0	0
T36	24424	0	0	0
T37	415267	0	0	0
T38	468804	0	0	0
T40	80711	8	0	0
T47	34069	1	0	0
T48	0	29	0	0
T49	0	25	0	0
T55	0	10	0	0
T157	0	25	0	0
T160	0	5	0	0
T161	0	15	0	0
T162	0	15	0	0
T163	0	15	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Unreachable
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	243852619	158	0	0
CgEnOn_A	243852619	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243852619	158	0	0
T1	828505	0	0	0
T2	26708	0	0	0
T4	17362	0	0	0
T7	5250	0	0	0
T19	0	1	0	0
T32	1635	2	0	0
T36	1485	0	0	0
T37	16550	0	0	0
T38	23702	0	0	0
T40	4438	0	0	0
T47	1864	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243852619	158	0	0
T1	828505	0	0	0
T2	26708	0	0	0
T4	17362	0	0	0
T7	5250	0	0	0
T19	0	1	0	0
T32	1635	2	0	0
T36	1485	0	0	0
T37	16550	0	0	0
T38	23702	0	0	0
T40	4438	0	0	0
T47	1864	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Unreachable
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	121925673	158	0	0
CgEnOn_A	121925673	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121925673	158	0	0
T1	414251	0	0	0
T2	13354	0	0	0
T4	8680	0	0	0
T7	2625	0	0	0
T19	0	1	0	0
T32	818	2	0	0
T36	740	0	0	0
T37	8275	0	0	0
T38	11851	0	0	0
T40	2219	0	0	0
T47	932	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121925673	158	0	0
T1	414251	0	0	0
T2	13354	0	0	0
T4	8680	0	0	0
T7	2625	0	0	0
T19	0	1	0	0
T32	818	2	0	0
T36	740	0	0	0
T37	8275	0	0	0
T38	11851	0	0	0
T40	2219	0	0	0
T47	932	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Unreachable
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	121925673	158	0	0
CgEnOn_A	121925673	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121925673	158	0	0
T1	414251	0	0	0
T2	13354	0	0	0
T4	8680	0	0	0
T7	2625	0	0	0
T19	0	1	0	0
T32	818	2	0	0
T36	740	0	0	0
T37	8275	0	0	0
T38	11851	0	0	0
T40	2219	0	0	0
T47	932	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121925673	158	0	0
T1	414251	0	0	0
T2	13354	0	0	0
T4	8680	0	0	0
T7	2625	0	0	0
T19	0	1	0	0
T32	818	2	0	0
T36	740	0	0	0
T37	8275	0	0	0
T38	11851	0	0	0
T40	2219	0	0	0
T47	932	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Unreachable
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	121925673	158	0	0
CgEnOn_A	121925673	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121925673	158	0	0
T1	414251	0	0	0
T2	13354	0	0	0
T4	8680	0	0	0
T7	2625	0	0	0
T19	0	1	0	0
T32	818	2	0	0
T36	740	0	0	0
T37	8275	0	0	0
T38	11851	0	0	0
T40	2219	0	0	0
T47	932	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121925673	158	0	0
T1	414251	0	0	0
T2	13354	0	0	0
T4	8680	0	0	0
T7	2625	0	0	0
T19	0	1	0	0
T32	818	2	0	0
T36	740	0	0	0
T37	8275	0	0	0
T38	11851	0	0	0
T40	2219	0	0	0
T47	932	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Unreachable
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	489171267	158	0	0
CgEnOn_A	489171267	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489171267	158	0	0
T1	165754	0	0	0
T2	53467	0	0	0
T4	71220	0	0	0
T7	10606	0	0	0
T19	0	1	0	0
T32	3309	2	0	0
T36	2673	0	0	0
T37	33193	0	0	0
T38	47456	0	0	0
T40	8982	0	0	0
T47	3794	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489171267	150	0	0
T1	165754	0	0	0
T2	53467	0	0	0
T4	71220	0	0	0
T7	10606	0	0	0
T32	3309	2	0	0
T36	2673	0	0	0
T37	33193	0	0	0
T38	47456	0	0	0
T40	8982	0	0	0
T47	3794	0	0	0
T48	0	3	0	0
T49	0	5	0	0
T55	0	2	0	0
T157	0	5	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	3	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Unreachable
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	522561045	140	0	0
CgEnOn_A	522561045	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	140	0	0
T1	175308	0	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	0	0	0
T47	3953	0	0	0
T48	0	5	0	0
T49	0	3	0	0
T55	0	3	0	0
T157	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	139	0	0
T1	175308	0	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	0	0	0
T47	3953	0	0	0
T48	0	5	0	0
T49	0	3	0	0
T55	0	3	0	0
T157	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Unreachable
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	522561045	140	0	0
CgEnOn_A	522561045	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	140	0	0
T1	175308	0	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	0	0	0
T47	3953	0	0	0
T48	0	5	0	0
T49	0	3	0	0
T55	0	3	0	0
T157	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	139	0	0
T1	175308	0	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	0	0	0
T47	3953	0	0	0
T48	0	5	0	0
T49	0	3	0	0
T55	0	3	0	0
T157	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Unreachable
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	250871035	152	0	0
CgEnOn_A	250871035	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250871035	152	0	0
T1	842072	0	0	0
T2	26734	0	0	0
T4	35612	0	0	0
T7	8183	0	0	0
T32	1564	4	0	0
T36	1336	0	0	0
T37	25237	0	0	0
T38	29489	0	0	0
T40	4492	0	0	0
T47	1897	0	0	0
T48	0	4	0	0
T49	0	4	0	0
T55	0	4	0	0
T157	0	2	0	0
T161	0	3	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250871035	151	0	0
T1	842072	0	0	0
T2	26734	0	0	0
T4	35612	0	0	0
T7	8183	0	0	0
T32	1564	4	0	0
T36	1336	0	0	0
T37	25237	0	0	0
T38	29489	0	0	0
T40	4492	0	0	0
T47	1897	0	0	0
T48	0	4	0	0
T49	0	4	0	0
T55	0	4	0	0
T157	0	2	0	0
T161	0	3	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T48,T49
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	121925673	8540	0	0
CgEnOn_A	121925673	6268	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121925673	8540	0	0
T5	45031	1	0	0
T6	15466	1	0	0
T8	432	10	0	0
T9	2483	1	0	0
T10	904	1	0	0
T28	4306	1	0	0
T29	321	11	0	0
T30	917	4	0	0
T31	1284	1	0	0
T32	818	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121925673	6268	0	0
T1	0	197	0	0
T5	45031	0	0	0
T6	15466	0	0	0
T8	432	9	0	0
T9	2483	0	0	0
T10	904	0	0	0
T14	0	40	0	0
T21	0	16	0	0
T24	0	1	0	0
T27	0	16	0	0
T28	4306	0	0	0
T29	321	10	0	0
T30	917	3	0	0
T31	1284	0	0	0
T32	818	2	0	0
T48	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T48,T49
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	243852619	8560	0	0
CgEnOn_A	243852619	6288	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243852619	8560	0	0
T5	90062	1	0	0
T6	30933	1	0	0
T8	863	10	0	0
T9	4970	1	0	0
T10	1811	1	0	0
T28	8613	1	0	0
T29	643	12	0	0
T30	1836	5	0	0
T31	2569	1	0	0
T32	1635	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243852619	6288	0	0
T1	0	194	0	0
T5	90062	0	0	0
T6	30933	0	0	0
T8	863	9	0	0
T9	4970	0	0	0
T10	1811	0	0	0
T14	0	45	0	0
T21	0	17	0	0
T24	0	1	0	0
T27	0	16	0	0
T28	8613	0	0	0
T29	643	11	0	0
T30	1836	4	0	0
T31	2569	0	0	0
T32	1635	2	0	0
T48	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T48,T49
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	489171267	8527	0	0
CgEnOn_A	489171267	6247	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489171267	8527	0	0
T5	180217	1	0	0
T6	61931	1	0	0
T8	1805	9	0	0
T9	8297	1	0	0
T10	3340	1	0	0
T28	17224	1	0	0
T29	1310	11	0	0
T30	3476	4	0	0
T31	4952	1	0	0
T32	3309	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489171267	6247	0	0
T1	0	184	0	0
T5	180217	0	0	0
T6	61931	0	0	0
T8	1805	8	0	0
T9	8297	0	0	0
T10	3340	0	0	0
T14	0	45	0	0
T21	0	14	0	0
T24	0	1	0	0
T27	0	17	0	0
T28	17224	0	0	0
T29	1310	10	0	0
T30	3476	3	0	0
T31	4952	0	0	0
T32	3309	2	0	0
T48	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T48,T49
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	250871035	8538	0	0
CgEnOn_A	250871035	6256	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250871035	8538	0	0
T5	90112	1	0	0
T6	30967	1	0	0
T8	902	14	0	0
T9	4149	1	0	0
T10	1670	1	0	0
T28	8612	1	0	0
T29	655	11	0	0
T30	1737	5	0	0
T31	2476	1	0	0
T32	1564	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250871035	6256	0	0
T1	0	188	0	0
T5	90112	0	0	0
T6	30967	0	0	0
T8	902	13	0	0
T9	4149	0	0	0
T10	1670	0	0	0
T14	0	46	0	0
T21	0	15	0	0
T24	0	1	0	0
T27	0	16	0	0
T28	8612	0	0	0
T29	655	10	0	0
T30	1737	4	0	0
T31	2476	0	0	0
T32	1564	4	0	0
T48	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Covered	T40,T47,T1
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	522561045	4346	0	0
CgEnOn_A	522561045	4345	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	4346	0	0
T1	175308	66	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T14	0	32	0	0
T24	0	1	0	0
T27	0	9	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	8	0	0
T47	3953	1	0	0
T48	0	5	0	0
T120	0	6	0	0
T121	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	4345	0	0
T1	175308	66	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T14	0	32	0	0
T24	0	1	0	0
T27	0	9	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	8	0	0
T47	3953	1	0	0
T48	0	5	0	0
T120	0	6	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Covered	T40,T1,T24
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	522561045	4282	0	0
CgEnOn_A	522561045	4281	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	4282	0	0
T1	175308	77	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T14	0	29	0	0
T24	0	1	0	0
T27	0	8	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	9	0	0
T47	3953	0	0	0
T48	0	5	0	0
T120	0	3	0	0
T121	0	1	0	0
T122	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	4281	0	0
T1	175308	77	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T14	0	29	0	0
T24	0	1	0	0
T27	0	8	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	9	0	0
T47	3953	0	0	0
T48	0	5	0	0
T120	0	3	0	0
T121	0	1	0	0
T122	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Covered	T40,T1,T24
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	522561045	4300	0	0
CgEnOn_A	522561045	4299	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	4300	0	0
T1	175308	75	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T14	0	35	0	0
T24	0	1	0	0
T27	0	7	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	8	0	0
T47	3953	0	0	0
T48	0	5	0	0
T120	0	5	0	0
T121	0	1	0	0
T122	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	4299	0	0
T1	175308	75	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T14	0	35	0	0
T24	0	1	0	0
T27	0	7	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	8	0	0
T47	3953	0	0	0
T48	0	5	0	0
T120	0	5	0	0
T121	0	1	0	0
T122	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T4,T1
1	0	Covered	T40,T47,T1
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	522561045	4324	0	0
CgEnOn_A	522561045	4323	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	4324	0	0
T1	175308	76	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T14	0	34	0	0
T24	0	1	0	0
T27	0	10	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	8	0	0
T47	3953	1	0	0
T48	0	5	0	0
T120	0	7	0	0
T121	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561045	4323	0	0
T1	175308	76	0	0
T2	55696	0	0	0
T4	74190	0	0	0
T7	17047	0	0	0
T14	0	34	0	0
T24	0	1	0	0
T27	0	10	0	0
T32	3385	3	0	0
T36	2785	0	0	0
T37	52577	0	0	0
T38	55434	0	0	0
T40	9357	8	0	0
T47	3953	1	0	0
T48	0	5	0	0
T120	0	7	0	0
T121	0	1	0	0