Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343933742

1

T5

2638

T6

2274

T7

6270

auto[1]

490826

1

T5

298

T21

238

T23

160

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343970046

1

T5

2774

T6

2274

T7

6270

auto[1]

454522

1

T5

162

T21

90

T23

114

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343802690

1

T5

2668

T6

2274

T7

6270

auto[1]

621878

1

T5

268

T21

208

T23

236

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319377334

1

T5

392

T6

2274

T7

6270

auto[1]

25047234

1

T5

2544

T21

3140

T23

170

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

208691922

1

T5

586

T6

2106

T7

3094

auto[1]

135732646

1

T5

2350

T6

168

T7

3176

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

186593798

1

T5

230

T6

2106

T7

3094

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

132376806

1

T6

168

T7

3176

T1

20

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

36668

1

T5

4

T23

22

T2

130

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8088

1

T13

36

T14

218

T62

36

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

21394268

1

T5

74

T21

2694

T23

56

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3216496

1

T5

2260

T21

166

T2

476

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59324

1

T5

10

T21

72

T2

180

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17940

1

T5

90

T2

38

T30

22

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

35778

1

T2

18

T30

16

T11

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1682

1

T11

22

T14

24

T63

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12334

1

T2

86

T11

102

T100

40

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3574

1

T11

70

T14

60

T78

82

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

12634

1

T30

20

T11

42

T12

24

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2612

1

T30

18

T12

8

T14

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

25544

1

T30

50

T11

76

T12

158

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5144

1

T12

50

T53

70

T55

308

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

86124

1

T5

2

T23

66

T31

74

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5332

1

T30

32

T31

6

T14

68

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

39812

1

T5

104

T23

56

T31

80

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8846

1

T31

72

T14

224

T62

70

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

36856

1

T21

4

T2

160

T30

48

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10184

1

T21

8

T2

80

T11

54

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

63128

1

T21

106

T2

234

T31

120

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16376

1

T11

68

T14

454

T63

36

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

89022

1

T5

52

T2

80

T30

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7616

1

T30

8

T31

60

T100

24

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

57956

1

T2

402

T31

60

T11

180

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13898

1

T100

64

T12

48

T13

96

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

51654

1

T5

20

T21

22

T23

32

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12880

1

T21

8

T2

46

T30

26

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

97022

1

T5

90

T21

60

T23

82

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

25172

1

T2

40

T30

38

T11

308