---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A	0	0	279009589	0	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21971486	0	0	0
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A	0	0	139504068	0	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21971486	0	0	0
tb.dut.u_io_meas.u_meas.MaxWidth_A	0	0	558717927	0	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21971486	0	0	0
tb.dut.u_main_meas.u_meas.MaxWidth_A	0	0	595751743	0	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21971486	0	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	280290249	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	140144402	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	561368002	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	598512351	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	287270380	0	0	1010
tb.dut.u_usb_meas.u_meas.MaxWidth_A	0	0	285945322	0	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21971486	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	174108063	171395822	0	0
tb.dut.AllClkBypReqKnownO_A	0	0	174108063	171395822	0	0
tb.dut.CgEnKnownO_A	0	0	174108063	171395822	0	0
tb.dut.ClocksKownO_A	0	0	174108063	171395822	0	0
tb.dut.FpvSecCmClkMainAesCountCheck_A	0	0	174108063	51	0	0
tb.dut.FpvSecCmClkMainHmacCountCheck_A	0	0	174108063	44	0	0
tb.dut.FpvSecCmClkMainKmacCountCheck_A	0	0	174108063	44	0	0
tb.dut.FpvSecCmClkMainOtbnCountCheck_A	0	0	174108063	46	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	174108063	80	0	0
tb.dut.IoClkBypReqKnownO_A	0	0	174108063	171395822	0	0
tb.dut.JitterEnableKnownO_A	0	0	174108063	171395822	0	0
tb.dut.LcCtrlClkBypAckKnownO_A	0	0	174108063	171395822	0	0
tb.dut.PwrMgrKnownO_A	0	0	174108063	171395822	0	0
tb.dut.TlAReadyKnownO_A	0	0	174108063	171395822	0	0
tb.dut.TlDValidKnownO_A	0	0	174108063	171395822	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A	0	0	595752187	4159	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A	0	0	595752187	2189	0	0
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A	0	0	279009589	164	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A	0	0	279009589	164	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A	0	0	279009589	8643	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A	0	0	279009589	6199	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A	0	0	139504068	164	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A	0	0	139504068	164	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A	0	0	139504068	8581	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A	0	0	139504068	6137	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A	0	0	139504068	164	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A	0	0	139504068	164	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A	0	0	139504068	164	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A	0	0	139504068	164	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOff_A	0	0	558717927	164	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOn_A	0	0	558717927	158	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOff_A	0	0	558717927	8662	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOn_A	0	0	558717927	6212	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOff_A	0	0	595751743	4325	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOn_A	0	0	595751743	4323	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A	0	0	595751743	4396	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A	0	0	595751743	4394	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOff_A	0	0	595751743	166	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOn_A	0	0	595751743	164	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A	0	0	595751743	4322	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A	0	0	595751743	4320	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A	0	0	595751743	4314	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A	0	0	595751743	4312	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOff_A	0	0	595751743	166	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOn_A	0	0	595751743	164	0	0
tb.dut.clkmgr_cg_usb_infra.CgEnOff_A	0	0	285945322	157	0	0
tb.dut.clkmgr_cg_usb_infra.CgEnOn_A	0	0	285945322	154	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A	0	0	285945322	8674	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A	0	0	285945322	6221	0	0
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A	0	0	175034241	5838358	0	0
tb.dut.clkmgr_csr_assert.clk_enables_rd_A	0	0	175034241	63496	0	0
tb.dut.clkmgr_csr_assert.clk_hints_rd_A	0	0	175034241	54867	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A	0	0	175034241	69993	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A	0	0	175034241	53857	0	0
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A	0	0	175034241	74764	0	0
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A	0	0	175034241	61124	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A	0	0	558718359	5379	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A	0	0	558718359	6097	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A	0	0	279009990	5313	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A	0	0	279009990	5918	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A	0	0	174108063	4786	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A	0	0	174108063	4786	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A	0	0	174108063	2854	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A	0	0	174108063	2854	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A	0	0	174108063	6015	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A	0	0	174108063	6015	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A	0	0	595752187	4230	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A	0	0	595752187	2169	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A	0	0	279009990	4029	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A	0	0	279009990	5819	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A	0	0	139504485	3812	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A	0	0	139504485	5602	0	0
tb.dut.clkmgr_io_peri_sva_if.GateClose_A	0	0	558718359	3996	0	0
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A	0	0	558718359	5790	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A	0	0	595752187	4156	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A	0	0	595752187	2238	0	0
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A	0	0	174108063	11309	0	0
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A	0	0	174108063	15060	0	0
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A	0	0	174108063	22455	0	0
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A	0	0	174108063	11147	0	0
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	174108063	19991385	0	64
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A	0	0	174108063	15211	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A	0	0	595752187	4148	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A	0	0	595752187	2169	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusFall_A	0	0	174108063	154	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusRise_A	0	0	174108063	154	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusFall_A	0	0	174108063	164	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusRise_A	0	0	174108063	164	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusFall_A	0	0	174108063	153	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusRise_A	0	0	174108063	153	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A	0	0	174108063	171236732	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A	0	0	174108063	156636	0	0
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	174108063	171143047	0	2415
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A	0	0	174108063	245413	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A	0	0	174108063	171249212	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A	0	0	174108063	144156	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A	0	0	285945723	4039	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A	0	0	285945723	5834	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	175034241	24436248	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	175034241	172212284	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	175034241	172212284	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	175034241	26059036	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	175034241	172212284	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	175034241	172212284	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
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tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	175034884	20151152	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	175034241	3143587	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	175034884	237824	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	175034884	136326	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	175034241	3477233	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	175034884	24436248	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	175034884	26059036	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	175034884	24436248	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	175034884	26059036	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	175034884	26059036	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	175034884	26059036	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	175034241	1877688	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	175034241	1427806	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1010	1010	0	0
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_calib_rdy_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	174108063	171395822	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	174108063	171395822	0	0
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	174108063	171395822	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	595751743	590773699	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	595751743	36270	0	0
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	595751743	590773699	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	595751743	36293	0	0
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	595751743	590773699	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	595751743	36202	0	0
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	595751743	590773699	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	595751743	36790	0	0
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	595751743	590781133	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	174108063	171395822	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	174108063	22413	0	0
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	174108063	19847	0	0
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	174108063	171395822	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	174108063	3414	0	0
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq	0	0	279009589	3414	0	0
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	279009589	4868633	0	0
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	279009589	117793	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21153873	115901	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	279009589	279009589	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	279009589	279009589	0	0
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	174108063	171395822	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	174108063	3310	0	0
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq	0	0	139504068	3310	0	0
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	139504068	4644649	0	0
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	139504068	115941	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21153873	114088	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	139504068	139504068	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	139504068	139504068	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	174108063	3567	0	0
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq	0	0	558717927	3567	0	0
tb.dut.u_io_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	558717927	4868732	0	0
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	558717927	118770	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21153873	116864	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	558717927	556349902	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	558717927	556349902	0	0
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_step_down_req_sync.OutputsKnown_A	0	0	558717927	554019293	0	0
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	558717927	554011931	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	558717927	31673	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	174108063	3148	0	0
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq	0	0	595751743	3148	0	0
tb.dut.u_main_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	595751743	4873978	0	0
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	595751743	141346	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21956658	141176	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	595751743	593248743	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	595751743	593248743	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0	0	0	278175560	278174755	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1	0	0	558717927	558717122	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	279009589	279008784	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	558717927	558717122	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	139504068	139503263	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	558717927	558717122	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A	0	0	279009589	277843792	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A	0	0	279009589	277843792	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A	0	0	139504068	138921234	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A	0	0	139504068	138921234	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A	0	0	139504068	138921234	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A	0	0	139504068	138921234	0	0
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A	0	0	558717927	554019293	0	0
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A	0	0	558717927	554019293	0	0
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A	0	0	595751743	590781133	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A	0	0	285945322	283567572	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A	0	0	285945322	283567572	0	0
tb.dut.u_reg.en2addrHit	0	0	175034241	935716	0	0
tb.dut.u_reg.reAfterRv	0	0	175034241	935716	0	0
tb.dut.u_reg.rePulse	0	0	175034241	212840	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	175034241	138663	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A	0	0	280290249	279078100	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	175034241	29808	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	280290249	1236	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	175034241	31044	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	280290249	29801	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	280290249	29808	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	29808	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	175034241	171410	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	280290249	279078100	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	175034241	35871	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	175034241	35870	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	280290249	35879	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	280290249	35877	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	35894	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	280290249	279078100	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	175034241	40	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	280290249	40	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	280290249	279078100	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	175034241	30	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	280290249	30	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	175034241	215610	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A	0	0	140144402	139538435	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	175034241	29808	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	140144402	1236	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	175034241	31044	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	140144402	29741	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	140144402	29808	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	29808	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	175034241	268536	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	140144402	139538435	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	175034241	35924	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	175034241	35922	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	140144402	35928	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	140144402	35925	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	35958	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	140144402	139538435	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	175034241	26	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	140144402	26	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	140144402	139538435	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	175034241	32	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	140144402	32	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	175034241	98823	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A	0	0	561368002	556487925	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	175034241	29808	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	561368002	1236	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	175034241	31044	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	561368002	29808	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	561368002	29808	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	29808	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	175034241	121564	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	561368002	556487925	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	175034241	36002	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	175034241	35999	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	561368002	36012	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	561368002	36008	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	36020	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	561368002	556487925	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	175034241	36	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	561368002	36	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	561368002	556487925	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	175034241	36	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	561368002	36	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	175034241	96503	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A	0	0	598512351	593352667	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	175034241	29808	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	598512351	1236	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	175034241	31044	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	598512351	29808	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	598512351	29808	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	29808	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	175034241	118177	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	598512351	593352667	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	175034241	35866	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	175034241	35862	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	598512351	35879	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	598512351	35877	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	35893	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	598512351	593352667	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	175034241	36	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	598512351	36	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	598512351	593352667	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	175034241	42	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	598512351	42	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	175034241	137338	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A	0	0	287270380	284801940	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	175034241	29255	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	287270380	1236	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	175034241	30491	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	287270380	29082	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	287270380	29275	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	29808	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	175034241	171500	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	287270380	284801940	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	175034241	35540	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	175034241	172212284	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	175034241	35512	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	287270380	35673	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	287270380	35619	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	175034241	35893	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	287270380	284801940	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	175034241	20	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	287270380	20	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	287270380	284801940	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	175034241	25	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	287270380	25	0	0
tb.dut.u_reg.wePulse	0	0	175034241	722876	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	174108063	171395822	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	174108063	3161	0	0
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq	0	0	285945322	3161	0	0
tb.dut.u_usb_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	285945322	4873907	0	0
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	285945322	139389	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21954596	139193	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	285945322	284749929	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	285945322	284749929	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	174108063	19991385	0	64
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	174108063	171143047	0	2415
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	595751743	590773699	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	595751743	590773699	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	595751743	590773699	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	595751743	590773699	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	558717927	554011931	0	2415
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	280290249	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	140144402	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	561368002	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	598512351	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	287270380	0	0	1010
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	174108063	171388181	0	2415

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	175034884	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	175034884	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	175034884	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	175034884	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	175034884	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	175034884	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	175034884	11731	11731	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	175034884	2811	2811	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	175034884	13044	13044	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	175034884	112316	112316	755

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	175034884	11731	11731	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	175034884	2811	2811	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	175034884	13044	13044	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	175034884	112316	112316	755