Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	627820	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3719909

1

T1

208

T7

13

T4

280

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1071769	1			T1	46		T7	10		T4	288
values[0x0]	1504856	1			T1	176		T7	9		T4	137
values[0x1]	1771104	1			T1	162		T7	12		T4	139

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	341847	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4005882

1

T1

271

T7

15

T4

350

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15822	1			T1	1		T5	1		T2	1
valid_sources[0x01]	17333	1			T1	1		T2	1		T116	2
valid_sources[0x02]	16530	1			T1	1		T5	4		T21	6
valid_sources[0x03]	16616	1			T1	3		T35	1		T29	1
valid_sources[0x04]	16882	1			T5	5		T19	1		T28	2
valid_sources[0x05]	16966	1			T1	1		T5	1		T2	2
valid_sources[0x06]	16898	1			T1	2		T5	4		T2	2
valid_sources[0x07]	16769	1			T1	1		T5	1		T2	1
valid_sources[0x08]	17673	1			T1	2		T2	1		T19	1
valid_sources[0x09]	16765	1			T5	2		T2	2		T29	1
valid_sources[0x0a]	17484	1			T1	1		T7	1		T5	3
valid_sources[0x0b]	16690	1			T1	4		T5	2		T21	1
valid_sources[0x0c]	16677	1			T1	2		T5	1		T21	10
valid_sources[0x0d]	18202	1			T2	3		T19	2		T26	5
valid_sources[0x0e]	18162	1			T1	2		T5	4		T19	1
valid_sources[0x0f]	16103	1			T1	1		T5	3		T2	2
valid_sources[0x10]	16287	1			T1	2		T2	1		T116	2
valid_sources[0x11]	16516	1			T1	1		T5	1		T2	3
valid_sources[0x12]	17769	1			T1	4		T5	1		T2	1
valid_sources[0x13]	15320	1			T1	2		T5	2		T2	4
valid_sources[0x14]	16993	1			T1	4		T2	3		T28	4
valid_sources[0x15]	16882	1			T1	1		T5	2		T116	3
valid_sources[0x16]	18228	1			T1	1		T5	2		T2	3
valid_sources[0x17]	16320	1			T5	2		T2	2		T21	6
valid_sources[0x18]	15473	1			T1	1		T5	4		T2	2
valid_sources[0x19]	16093	1			T1	3		T5	1		T2	1
valid_sources[0x1a]	18170	1			T5	1		T3	7		T10	356
valid_sources[0x1b]	17578	1			T1	2		T5	2		T2	1
valid_sources[0x1c]	16495	1			T7	6		T5	1		T29	1
valid_sources[0x1d]	16216	1			T1	1		T5	2		T21	1
valid_sources[0x1e]	17575	1			T1	2		T5	4		T35	1
valid_sources[0x1f]	18612	1			T1	1		T5	6		T26	6
valid_sources[0x20]	16078	1			T5	4		T2	3		T25	2
valid_sources[0x21]	15813	1			T1	2		T5	10		T3	6
valid_sources[0x22]	17047	1			T1	1		T5	1		T21	2
valid_sources[0x23]	19734	1			T1	1		T26	1		T3	3
valid_sources[0x24]	17492	1			T1	3		T5	1		T3	2
valid_sources[0x25]	16021	1			T5	2		T25	5		T3	6
valid_sources[0x26]	15107	1			T1	2		T5	1		T2	8
valid_sources[0x27]	16812	1			T1	2		T5	1		T26	6
valid_sources[0x28]	15761	1			T1	1		T5	6		T29	1
valid_sources[0x29]	16166	1			T1	1		T5	4		T3	5
valid_sources[0x2a]	17553	1			T1	1		T5	5		T2	4
valid_sources[0x2b]	17453	1			T1	2		T5	3		T3	1
valid_sources[0x2c]	19052	1			T1	2		T2	3		T3	5
valid_sources[0x2d]	16557	1			T5	1		T35	1		T3	5
valid_sources[0x2e]	17004	1			T1	1		T5	1		T2	1
valid_sources[0x2f]	17621	1			T1	1		T5	4		T2	1
valid_sources[0x30]	16282	1			T1	3		T5	2		T2	2
valid_sources[0x31]	17163	1			T1	2		T5	5		T2	2
valid_sources[0x32]	17740	1			T1	4		T26	1		T3	1
valid_sources[0x33]	16836	1			T1	1		T5	8		T2	4
valid_sources[0x34]	16803	1			T1	2		T5	5		T2	1
valid_sources[0x35]	16937	1			T5	2		T2	1		T19	1
valid_sources[0x36]	17591	1			T1	1		T5	5		T3	3
valid_sources[0x37]	17297	1			T1	1		T26	2		T3	4
valid_sources[0x38]	20102	1			T1	1		T5	1		T35	2
valid_sources[0x39]	17394	1			T1	1		T5	4		T2	1
valid_sources[0x3a]	16406	1			T1	2		T5	4		T2	1
valid_sources[0x3b]	16708	1			T1	2		T5	4		T2	1
valid_sources[0x3c]	17056	1			T1	1		T5	5		T2	2
valid_sources[0x3d]	16157	1			T1	1		T5	5		T2	2
valid_sources[0x3e]	16868	1			T1	3		T5	2		T35	1
valid_sources[0x3f]	17636	1			T1	1		T5	2		T2	2
valid_sources[0x40]	18488	1			T1	1		T5	2		T2	1
valid_sources[0x41]	16251	1			T1	1		T5	3		T2	2
valid_sources[0x42]	17122	1			T1	2		T5	3		T2	5
valid_sources[0x43]	17530	1			T5	1		T19	1		T25	1
valid_sources[0x44]	18138	1			T1	1		T5	2		T2	1
valid_sources[0x45]	17656	1			T1	2		T2	2		T3	6
valid_sources[0x46]	18285	1			T7	5		T5	2		T2	1
valid_sources[0x47]	16518	1			T1	1		T5	1		T3	6
valid_sources[0x48]	16020	1			T2	2		T3	9		T10	165
valid_sources[0x49]	16725	1			T1	1		T5	5		T35	1
valid_sources[0x4a]	17353	1			T1	2		T5	1		T26	4
valid_sources[0x4b]	18188	1			T1	2		T4	564		T5	3
valid_sources[0x4c]	15253	1			T1	1		T35	1		T29	1
valid_sources[0x4d]	16046	1			T5	1		T2	3		T19	1
valid_sources[0x4e]	15858	1			T1	1		T5	1		T3	5
valid_sources[0x4f]	18051	1			T2	2		T21	1		T25	1
valid_sources[0x50]	16300	1			T1	1		T7	4		T5	2
valid_sources[0x51]	17092	1			T5	2		T3	4		T10	50
valid_sources[0x52]	16741	1			T1	5		T5	5		T19	1
valid_sources[0x53]	16614	1			T5	1		T2	1		T21	1
valid_sources[0x54]	16161	1			T1	1		T5	1		T21	6
valid_sources[0x55]	18239	1			T1	1		T7	5		T5	2
valid_sources[0x56]	15630	1			T1	1		T5	6		T2	1
valid_sources[0x57]	15907	1			T5	1		T2	1		T25	2
valid_sources[0x58]	16874	1			T1	3		T2	2		T116	12
valid_sources[0x59]	16050	1			T1	1		T5	2		T2	1
valid_sources[0x5a]	16170	1			T1	3		T5	1		T2	4
valid_sources[0x5b]	15621	1			T1	2		T5	2		T2	1
valid_sources[0x5c]	16695	1			T5	1		T19	1		T29	1
valid_sources[0x5d]	18307	1			T1	1		T5	1		T21	1
valid_sources[0x5e]	18075	1			T5	3		T35	1		T3	6
valid_sources[0x5f]	16625	1			T1	1		T5	3		T21	1
valid_sources[0x60]	18616	1			T1	4		T3	6		T10	290
valid_sources[0x61]	16368	1			T1	3		T2	2		T19	1
valid_sources[0x62]	18110	1			T5	2		T2	1		T116	1
valid_sources[0x63]	17056	1			T1	2		T5	4		T2	2
valid_sources[0x64]	17341	1			T1	3		T7	5		T5	2
valid_sources[0x65]	17517	1			T1	1		T5	5		T2	2
valid_sources[0x66]	18820	1			T1	2		T5	3		T3	5
valid_sources[0x67]	16298	1			T1	5		T5	4		T2	1
valid_sources[0x68]	15393	1			T1	1		T2	3		T3	4
valid_sources[0x69]	17283	1			T5	4		T2	4		T3	5
valid_sources[0x6a]	17990	1			T1	2		T5	4		T21	2
valid_sources[0x6b]	18853	1			T1	2		T5	5		T2	2
valid_sources[0x6c]	17465	1			T1	3		T5	4		T2	2
valid_sources[0x6d]	17505	1			T1	1		T5	5		T116	1
valid_sources[0x6e]	19215	1			T1	4		T5	1		T21	1
valid_sources[0x6f]	16167	1			T10	192		T68	1		T12	159
valid_sources[0x70]	18116	1			T1	1		T5	3		T21	2
valid_sources[0x71]	16774	1			T1	2		T26	3		T3	4
valid_sources[0x72]	17876	1			T1	1		T5	3		T3	3
valid_sources[0x73]	18320	1			T1	2		T5	2		T2	1
valid_sources[0x74]	16224	1			T1	1		T26	4		T3	7
valid_sources[0x75]	17329	1			T1	3		T5	2		T2	1
valid_sources[0x76]	16458	1			T1	3		T5	5		T21	2
valid_sources[0x77]	17958	1			T1	2		T5	1		T2	1
valid_sources[0x78]	17319	1			T1	2		T5	1		T25	2
valid_sources[0x79]	16504	1			T1	3		T5	3		T35	1
valid_sources[0x7a]	17988	1			T1	1		T26	8		T3	4
valid_sources[0x7b]	16342	1			T1	1		T5	1		T2	2
valid_sources[0x7c]	16725	1			T1	1		T5	1		T2	2
valid_sources[0x7d]	15748	1			T5	5		T26	1		T3	6
valid_sources[0x7e]	16933	1			T1	2		T3	11		T10	92
valid_sources[0x7f]	19001	1			T5	1		T3	3		T10	54
valid_sources[0x80]	16728	1			T1	1		T5	1		T2	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

941342

1

T1

22

T7

7

T4

143

values[0x0]

all_enables

biggest_size

1412264

1

T1

128

T7

5

T4

87

values[0x1]

all_enables

biggest_size

1366303

1

T1

58

T7

1

T4

50