Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg
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Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
PeriDiv2 100.00 1 100 1 64 64
PeriDiv4 100.00 1 100 1 64 64
PeriIo 100.00 1 100 1 64 64
PeriUsb 100.00 1 100 1 64 64




Group Instance : PeriDiv2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriDiv2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriDiv2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriDiv2
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0



Group Instance : PeriDiv4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriDiv4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriDiv4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriDiv4
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0



Group Instance : PeriIo
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriIo

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriIo
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriIo
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0



Group Instance : PeriUsb
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance PeriUsb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group Instance PeriUsb
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_enable_cp 2 0 2 100.00 100 1 1 2
ip_clk_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance PeriUsb
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
peri_cross 6 0 6 100.00 100 1 1 0


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 275740 1 T6 2 T1 2 T7 2
auto[1] 213078182 1 T6 676 T1 90170 T7 983



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8991 1 T6 47 T1 2 T7 2
auto[1] 213344931 1 T6 631 T1 90170 T7 983



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 102556421 1 T6 678 T1 90166 T7 288
auto[1] 110797501 1 T1 6 T7 697 T18 669



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5576 1 T6 2 T4 26 T5 28
auto[0] auto[0] auto[1] 1584 1 T1 2 T7 2 T18 2
auto[0] auto[1] auto[0] 207093 1 T72 22 T3 478 T10 832
auto[0] auto[1] auto[1] 61487 1 T72 22 T3 630 T10 1014
auto[1] auto[1] auto[0] 102341921 1 T6 631 T1 90166 T7 288
auto[1] auto[1] auto[1] 110734430 1 T1 4 T7 695 T18 667


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 142081 1 T6 2 T1 2 T7 2
auto[1] 106532851 1 T6 337 T1 45084 T7 489



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8070 1 T6 25 T1 2 T7 2
auto[1] 106666862 1 T6 314 T1 45084 T7 489



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 51276262 1 T6 339 T1 45083 T7 142
auto[1] 55398670 1 T1 3 T7 349 T18 335



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5576 1 T6 2 T4 26 T5 28
auto[0] auto[0] auto[1] 1584 1 T1 2 T7 2 T18 2
auto[0] auto[1] auto[0] 105002 1 T72 8 T3 227 T10 430
auto[0] auto[1] auto[1] 29919 1 T72 15 T3 339 T10 465
auto[1] auto[1] auto[0] 51164774 1 T6 314 T1 45083 T7 142
auto[1] auto[1] auto[1] 55367167 1 T1 1 T7 347 T18 333


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 559188 1 T6 2 T1 2 T7 2
auto[1] 425180708 1 T6 1354 T1 180341 T7 1892



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10815 1 T6 89 T1 2 T7 2
auto[1] 425729081 1 T6 1267 T1 180341 T7 1892



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 204144979 1 T6 1356 T1 180332 T7 500
auto[1] 221594917 1 T1 11 T7 1394 T18 1339



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5576 1 T6 2 T4 26 T5 28
auto[0] auto[0] auto[1] 1584 1 T1 2 T7 2 T18 2
auto[0] auto[1] auto[0] 431855 1 T72 31 T3 904 T10 1781
auto[0] auto[1] auto[1] 120173 1 T72 59 T3 1331 T10 1883
auto[1] auto[1] auto[0] 203703893 1 T6 1267 T1 180332 T7 500
auto[1] auto[1] auto[1] 221473160 1 T1 9 T7 1392 T18 1337


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded


Summary for Variable csr_enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 289241 1 T6 2 T1 2 T7 2
auto[1] 217409517 1 T6 594 T1 90174 T7 944



Summary for Variable ip_clk_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for ip_clk_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8759 1 T6 20 T1 2 T7 2
auto[1] 217689999 1 T6 576 T1 90174 T7 944



Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 104972123 1 T6 596 T1 90170 T7 249
auto[1] 112726635 1 T1 6 T7 697 T18 670



Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for peri_cross

Bins
csr_enable_cpip_clk_en_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 5566 1 T6 2 T4 26 T5 28
auto[0] auto[0] auto[1] 1594 1 T1 2 T7 2 T18 2
auto[0] auto[1] auto[0] 221998 1 T72 23 T3 455 T10 915
auto[0] auto[1] auto[1] 60083 1 T72 22 T3 661 T10 886
auto[1] auto[1] auto[0] 104742960 1 T6 576 T1 90170 T7 249
auto[1] auto[1] auto[1] 112664958 1 T1 4 T7 695 T18 668


User Defined Cross Bins for peri_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore_enable_off 0 Excluded

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