Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T5
0	1	Covered	T72,T3,T10
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T22
1	0	Covered	T6,T17,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	965958280	13694	0	0
GateOpen_A	965958280	20523	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965958280	13694	0	0
T1	406113	0	0	0
T2	275472	0	0	0
T3	0	70	0	0
T4	139380	0	0	0
T5	234576	0	0	0
T6	3449	25	0	0
T7	4734	0	0	0
T10	0	255	0	0
T12	0	190	0	0
T17	3860	14	0	0
T18	3530	0	0	0
T19	5886	0	0	0
T20	12611	0	0	0
T36	0	8	0	0
T65	0	32	0	0
T70	0	10	0	0
T72	0	15	0	0
T150	0	13	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965958280	20523	0	0
T1	406113	0	0	0
T2	275472	4	0	0
T4	139380	52	0	0
T5	234576	56	0	0
T6	3449	29	0	0
T7	4734	0	0	0
T17	3860	18	0	0
T18	3530	0	0	0
T19	5886	4	0	0
T20	12611	0	0	0
T22	0	8	0	0
T35	0	4	0	0
T72	0	15	0	0
T73	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T5
0	1	Covered	T72,T3,T10
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T22
1	0	Covered	T6,T17,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	106613261	3224	0	0
GateOpen_A	106613261	4930	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106613261	3224	0	0
T1	45110	0	0	0
T2	30597	0	0	0
T3	0	17	0	0
T4	11155	0	0	0
T5	19337	0	0	0
T6	370	7	0	0
T7	516	0	0	0
T10	0	59	0	0
T12	0	46	0	0
T17	409	3	0	0
T18	386	0	0	0
T19	646	0	0	0
T20	1391	0	0	0
T36	0	2	0	0
T65	0	6	0	0
T70	0	2	0	0
T72	0	3	0	0
T150	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106613261	4930	0	0
T1	45110	0	0	0
T2	30597	1	0	0
T4	11155	13	0	0
T5	19337	14	0	0
T6	370	8	0	0
T7	516	0	0	0
T17	409	4	0	0
T18	386	0	0	0
T19	646	1	0	0
T20	1391	0	0	0
T22	0	2	0	0
T35	0	1	0	0
T72	0	3	0	0
T73	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T5
0	1	Covered	T72,T3,T10
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T22
1	0	Covered	T6,T17,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	213227515	3477	0	0
GateOpen_A	213227515	5183	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227515	3477	0	0
T1	90220	0	0	0
T2	61194	0	0	0
T3	0	17	0	0
T4	22309	0	0	0
T5	38671	0	0	0
T6	740	7	0	0
T7	1031	0	0	0
T10	0	65	0	0
T12	0	47	0	0
T17	817	3	0	0
T18	772	0	0	0
T19	1291	0	0	0
T20	2781	0	0	0
T36	0	2	0	0
T65	0	8	0	0
T70	0	3	0	0
T72	0	4	0	0
T150	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227515	5183	0	0
T1	90220	0	0	0
T2	61194	1	0	0
T4	22309	13	0	0
T5	38671	14	0	0
T6	740	8	0	0
T7	1031	0	0	0
T17	817	4	0	0
T18	772	0	0	0
T19	1291	1	0	0
T20	2781	0	0	0
T22	0	2	0	0
T35	0	1	0	0
T72	0	4	0	0
T73	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T5
0	1	Covered	T72,T3,T10
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T22
1	0	Covered	T6,T17,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	427507459	3512	0	0
GateOpen_A	427507459	5219	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507459	3512	0	0
T1	180519	0	0	0
T2	122452	0	0	0
T3	0	18	0	0
T4	70610	0	0	0
T5	117710	0	0	0
T6	1614	7	0	0
T7	2124	0	0	0
T10	0	70	0	0
T12	0	49	0	0
T17	1754	3	0	0
T18	1582	0	0	0
T19	2633	0	0	0
T20	5626	0	0	0
T36	0	2	0	0
T65	0	10	0	0
T70	0	3	0	0
T72	0	4	0	0
T150	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507459	5219	0	0
T1	180519	0	0	0
T2	122452	1	0	0
T4	70610	13	0	0
T5	117710	14	0	0
T6	1614	8	0	0
T7	2124	0	0	0
T17	1754	4	0	0
T18	1582	0	0	0
T19	2633	1	0	0
T20	5626	0	0	0
T22	0	2	0	0
T35	0	1	0	0
T72	0	4	0	0
T73	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T5
0	1	Covered	T72,T3,T10
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T22
1	0	Covered	T6,T17,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	218610045	3481	0	0
GateOpen_A	218610045	5191	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218610045	3481	0	0
T1	90264	0	0	0
T2	61229	0	0	0
T3	0	18	0	0
T4	35306	0	0	0
T5	58858	0	0	0
T6	725	4	0	0
T7	1063	0	0	0
T10	0	61	0	0
T12	0	48	0	0
T17	880	5	0	0
T18	790	0	0	0
T19	1316	0	0	0
T20	2813	0	0	0
T36	0	2	0	0
T65	0	8	0	0
T70	0	2	0	0
T72	0	4	0	0
T150	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218610045	5191	0	0
T1	90264	0	0	0
T2	61229	1	0	0
T4	35306	13	0	0
T5	58858	14	0	0
T6	725	5	0	0
T7	1063	0	0	0
T17	880	6	0	0
T18	790	0	0	0
T19	1316	1	0	0
T20	2813	0	0	0
T22	0	2	0	0
T35	0	1	0	0
T72	0	4	0	0
T73	0	1	0	0