Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	836361935	73560	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	836361935	73560	0	0
T1	940230	405	0	0
T2	605920	192	0	0
T3	0	180	0	0
T4	47810	0	0	0
T5	104220	0	0	0
T7	10845	0	0	0
T10	0	1077	0	0
T11	0	610	0	0
T12	0	485	0	0
T13	0	346	0	0
T14	0	291	0	0
T15	0	220	0	0
T16	0	205	0	0
T17	7820	0	0	0
T18	8235	0	0	0
T19	8090	0	0	0
T20	7320	0	0	0
T21	11005	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167272387	10601	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	10601	0	0
T1	188046	52	0	0
T2	121184	25	0	0
T3	0	29	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T7	2169	0	0	0
T10	0	145	0	0
T11	0	81	0	0
T12	0	78	0	0
T13	0	56	0	0
T14	0	56	0	0
T15	0	35	0	0
T16	0	41	0	0
T17	1564	0	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T21	2201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167272387	10581	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	10581	0	0
T1	188046	59	0	0
T2	121184	25	0	0
T3	0	29	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T7	2169	0	0	0
T10	0	145	0	0
T11	0	79	0	0
T12	0	78	0	0
T13	0	55	0	0
T14	0	56	0	0
T15	0	35	0	0
T16	0	41	0	0
T17	1564	0	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T21	2201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167272387	14776	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	14776	0	0
T1	188046	80	0	0
T2	121184	39	0	0
T3	0	37	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T7	2169	0	0	0
T10	0	217	0	0
T11	0	121	0	0
T12	0	98	0	0
T13	0	70	0	0
T14	0	56	0	0
T15	0	45	0	0
T16	0	41	0	0
T17	1564	0	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T21	2201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167272387	14756	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	14756	0	0
T1	188046	80	0	0
T2	121184	39	0	0
T3	0	37	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T7	2169	0	0	0
T10	0	216	0	0
T11	0	122	0	0
T12	0	98	0	0
T13	0	70	0	0
T14	0	56	0	0
T15	0	46	0	0
T16	0	41	0	0
T17	1564	0	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T21	2201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167272387	22846	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	22846	0	0
T1	188046	134	0	0
T2	121184	64	0	0
T3	0	48	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T7	2169	0	0	0
T10	0	354	0	0
T11	0	207	0	0
T12	0	133	0	0
T13	0	95	0	0
T14	0	67	0	0
T15	0	59	0	0
T16	0	41	0	0
T17	1564	0	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T21	2201	0	0	0