Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22512 |
22512 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4911690 |
4907285 |
0 |
0 |
T2 |
3242521 |
3240187 |
0 |
0 |
T4 |
1005843 |
329338 |
0 |
0 |
T5 |
1747661 |
736127 |
0 |
0 |
T6 |
44316 |
37980 |
0 |
0 |
T7 |
57138 |
51356 |
0 |
0 |
T17 |
44060 |
38969 |
0 |
0 |
T18 |
42990 |
41307 |
0 |
0 |
T19 |
55845 |
52315 |
0 |
0 |
T20 |
91471 |
89201 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1003634322 |
989427666 |
0 |
14472 |
T1 |
1128276 |
1127160 |
0 |
18 |
T2 |
727104 |
726534 |
0 |
18 |
T4 |
57372 |
12972 |
0 |
18 |
T5 |
125064 |
43122 |
0 |
18 |
T6 |
10470 |
8916 |
0 |
18 |
T7 |
13014 |
11586 |
0 |
18 |
T17 |
9384 |
8238 |
0 |
18 |
T18 |
9882 |
9450 |
0 |
18 |
T19 |
9708 |
8994 |
0 |
18 |
T20 |
8784 |
8514 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16884 |
T1 |
1308795 |
1307500 |
0 |
21 |
T2 |
875052 |
874361 |
0 |
21 |
T4 |
383950 |
88090 |
0 |
21 |
T5 |
649869 |
224709 |
0 |
21 |
T6 |
11692 |
9825 |
0 |
21 |
T7 |
15314 |
13633 |
0 |
21 |
T17 |
12238 |
10650 |
0 |
21 |
T18 |
11463 |
10962 |
0 |
21 |
T19 |
16836 |
15602 |
0 |
21 |
T20 |
31994 |
31051 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
195427 |
0 |
0 |
T1 |
752184 |
4 |
0 |
0 |
T2 |
631416 |
4 |
0 |
0 |
T3 |
86856 |
119 |
0 |
0 |
T4 |
303778 |
52 |
0 |
0 |
T5 |
511316 |
56 |
0 |
0 |
T6 |
6588 |
63 |
0 |
0 |
T7 |
11021 |
83 |
0 |
0 |
T10 |
263330 |
407 |
0 |
0 |
T11 |
0 |
65 |
0 |
0 |
T12 |
0 |
309 |
0 |
0 |
T13 |
0 |
31 |
0 |
0 |
T17 |
8920 |
54 |
0 |
0 |
T18 |
8235 |
19 |
0 |
0 |
T19 |
12586 |
12 |
0 |
0 |
T20 |
24904 |
65 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T22 |
9955 |
0 |
0 |
0 |
T25 |
13187 |
0 |
0 |
0 |
T26 |
83642 |
0 |
0 |
0 |
T28 |
2566 |
79 |
0 |
0 |
T29 |
1602 |
77 |
0 |
0 |
T36 |
716 |
0 |
0 |
0 |
T65 |
1463 |
0 |
0 |
0 |
T66 |
0 |
150 |
0 |
0 |
T71 |
0 |
16 |
0 |
0 |
T107 |
0 |
138 |
0 |
0 |
T116 |
3033 |
0 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2474619 |
2472586 |
0 |
0 |
T2 |
1640365 |
1639253 |
0 |
0 |
T4 |
564521 |
227769 |
0 |
0 |
T5 |
972728 |
467750 |
0 |
0 |
T6 |
22154 |
19200 |
0 |
0 |
T7 |
28810 |
26098 |
0 |
0 |
T17 |
22438 |
20042 |
0 |
0 |
T18 |
21645 |
20856 |
0 |
0 |
T19 |
29301 |
27680 |
0 |
0 |
T20 |
50693 |
49597 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T7,T28,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T7,T28,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T7,T28,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T7,T28,T29 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T28,T29 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T28,T29 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T28,T29 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T28,T29 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427507042 |
423502839 |
0 |
0 |
T1 |
180519 |
180343 |
0 |
0 |
T2 |
122452 |
122358 |
0 |
0 |
T4 |
70610 |
16249 |
0 |
0 |
T5 |
117709 |
40749 |
0 |
0 |
T6 |
1614 |
1356 |
0 |
0 |
T7 |
2124 |
1894 |
0 |
0 |
T17 |
1754 |
1523 |
0 |
0 |
T18 |
1581 |
1515 |
0 |
0 |
T19 |
2632 |
2443 |
0 |
0 |
T20 |
5626 |
5464 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427507042 |
423495641 |
0 |
2412 |
T1 |
180519 |
180340 |
0 |
3 |
T2 |
122452 |
122355 |
0 |
3 |
T4 |
70610 |
16210 |
0 |
3 |
T5 |
117709 |
40707 |
0 |
3 |
T6 |
1614 |
1353 |
0 |
3 |
T7 |
2124 |
1891 |
0 |
3 |
T17 |
1754 |
1520 |
0 |
3 |
T18 |
1581 |
1512 |
0 |
3 |
T19 |
2632 |
2440 |
0 |
3 |
T20 |
5626 |
5461 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427507042 |
28600 |
0 |
0 |
T2 |
122452 |
0 |
0 |
0 |
T3 |
0 |
46 |
0 |
0 |
T4 |
70610 |
0 |
0 |
0 |
T5 |
117709 |
0 |
0 |
0 |
T7 |
2124 |
19 |
0 |
0 |
T10 |
0 |
172 |
0 |
0 |
T11 |
0 |
31 |
0 |
0 |
T12 |
0 |
131 |
0 |
0 |
T17 |
1754 |
0 |
0 |
0 |
T18 |
1581 |
0 |
0 |
0 |
T19 |
2632 |
0 |
0 |
0 |
T20 |
5626 |
0 |
0 |
0 |
T21 |
8455 |
0 |
0 |
0 |
T22 |
9557 |
0 |
0 |
0 |
T28 |
0 |
36 |
0 |
0 |
T29 |
0 |
35 |
0 |
0 |
T66 |
0 |
62 |
0 |
0 |
T71 |
0 |
8 |
0 |
0 |
T107 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T28,T29,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T28,T29,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T28,T29,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T28,T29,T3 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T28,T29,T3 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T28,T29,T3 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T28,T29,T3 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T28,T29,T3 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164904611 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
121184 |
121089 |
0 |
3 |
T4 |
9562 |
2162 |
0 |
3 |
T5 |
20844 |
7187 |
0 |
3 |
T6 |
1745 |
1486 |
0 |
3 |
T7 |
2169 |
1931 |
0 |
3 |
T17 |
1564 |
1373 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
1618 |
1499 |
0 |
3 |
T20 |
1464 |
1419 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
17541 |
0 |
0 |
T3 |
86856 |
40 |
0 |
0 |
T10 |
263330 |
111 |
0 |
0 |
T11 |
0 |
19 |
0 |
0 |
T12 |
0 |
84 |
0 |
0 |
T13 |
0 |
31 |
0 |
0 |
T25 |
13187 |
0 |
0 |
0 |
T26 |
83642 |
0 |
0 |
0 |
T27 |
17002 |
0 |
0 |
0 |
T28 |
2566 |
25 |
0 |
0 |
T29 |
1602 |
3 |
0 |
0 |
T36 |
716 |
0 |
0 |
0 |
T65 |
1463 |
0 |
0 |
0 |
T66 |
0 |
40 |
0 |
0 |
T71 |
0 |
4 |
0 |
0 |
T107 |
0 |
50 |
0 |
0 |
T116 |
3033 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T7,T28,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T7,T28,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T7,T28,T29 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T7,T28,T29 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T28,T29 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T28,T29 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T28,T29 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T28,T29 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164904611 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
121184 |
121089 |
0 |
3 |
T4 |
9562 |
2162 |
0 |
3 |
T5 |
20844 |
7187 |
0 |
3 |
T6 |
1745 |
1486 |
0 |
3 |
T7 |
2169 |
1931 |
0 |
3 |
T17 |
1564 |
1373 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
1618 |
1499 |
0 |
3 |
T20 |
1464 |
1419 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
20231 |
0 |
0 |
T2 |
121184 |
0 |
0 |
0 |
T3 |
0 |
33 |
0 |
0 |
T4 |
9562 |
0 |
0 |
0 |
T5 |
20844 |
0 |
0 |
0 |
T7 |
2169 |
22 |
0 |
0 |
T10 |
0 |
124 |
0 |
0 |
T11 |
0 |
15 |
0 |
0 |
T12 |
0 |
94 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T22 |
9955 |
0 |
0 |
0 |
T28 |
0 |
18 |
0 |
0 |
T29 |
0 |
39 |
0 |
0 |
T66 |
0 |
48 |
0 |
0 |
T71 |
0 |
4 |
0 |
0 |
T107 |
0 |
48 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
453716265 |
0 |
0 |
T1 |
188046 |
187963 |
0 |
0 |
T2 |
127558 |
127489 |
0 |
0 |
T4 |
73554 |
46471 |
0 |
0 |
T5 |
122618 |
80563 |
0 |
0 |
T6 |
1647 |
1507 |
0 |
0 |
T7 |
2213 |
2073 |
0 |
0 |
T17 |
1839 |
1713 |
0 |
0 |
T18 |
1647 |
1606 |
0 |
0 |
T19 |
2742 |
2687 |
0 |
0 |
T20 |
5860 |
5791 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
453716265 |
0 |
0 |
T1 |
188046 |
187963 |
0 |
0 |
T2 |
127558 |
127489 |
0 |
0 |
T4 |
73554 |
46471 |
0 |
0 |
T5 |
122618 |
80563 |
0 |
0 |
T6 |
1647 |
1507 |
0 |
0 |
T7 |
2213 |
2073 |
0 |
0 |
T17 |
1839 |
1713 |
0 |
0 |
T18 |
1647 |
1606 |
0 |
0 |
T19 |
2742 |
2687 |
0 |
0 |
T20 |
5860 |
5791 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427507042 |
425490831 |
0 |
0 |
T1 |
180519 |
180439 |
0 |
0 |
T2 |
122452 |
122386 |
0 |
0 |
T4 |
70610 |
44610 |
0 |
0 |
T5 |
117709 |
77338 |
0 |
0 |
T6 |
1614 |
1479 |
0 |
0 |
T7 |
2124 |
1990 |
0 |
0 |
T17 |
1754 |
1633 |
0 |
0 |
T18 |
1581 |
1542 |
0 |
0 |
T19 |
2632 |
2580 |
0 |
0 |
T20 |
5626 |
5560 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427507042 |
425490831 |
0 |
0 |
T1 |
180519 |
180439 |
0 |
0 |
T2 |
122452 |
122386 |
0 |
0 |
T4 |
70610 |
44610 |
0 |
0 |
T5 |
117709 |
77338 |
0 |
0 |
T6 |
1614 |
1479 |
0 |
0 |
T7 |
2124 |
1990 |
0 |
0 |
T17 |
1754 |
1633 |
0 |
0 |
T18 |
1581 |
1542 |
0 |
0 |
T19 |
2632 |
2580 |
0 |
0 |
T20 |
5626 |
5560 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
213227110 |
213227110 |
0 |
0 |
T1 |
90220 |
90220 |
0 |
0 |
T2 |
61193 |
61193 |
0 |
0 |
T4 |
22309 |
22309 |
0 |
0 |
T5 |
38671 |
38671 |
0 |
0 |
T6 |
740 |
740 |
0 |
0 |
T7 |
1030 |
1030 |
0 |
0 |
T17 |
817 |
817 |
0 |
0 |
T18 |
771 |
771 |
0 |
0 |
T19 |
1290 |
1290 |
0 |
0 |
T20 |
2780 |
2780 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
213227110 |
213227110 |
0 |
0 |
T1 |
90220 |
90220 |
0 |
0 |
T2 |
61193 |
61193 |
0 |
0 |
T4 |
22309 |
22309 |
0 |
0 |
T5 |
38671 |
38671 |
0 |
0 |
T6 |
740 |
740 |
0 |
0 |
T7 |
1030 |
1030 |
0 |
0 |
T17 |
817 |
817 |
0 |
0 |
T18 |
771 |
771 |
0 |
0 |
T19 |
1290 |
1290 |
0 |
0 |
T20 |
2780 |
2780 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
106612844 |
106612844 |
0 |
0 |
T1 |
45110 |
45110 |
0 |
0 |
T2 |
30597 |
30597 |
0 |
0 |
T4 |
11154 |
11154 |
0 |
0 |
T5 |
19337 |
19337 |
0 |
0 |
T6 |
370 |
370 |
0 |
0 |
T7 |
515 |
515 |
0 |
0 |
T17 |
408 |
408 |
0 |
0 |
T18 |
386 |
386 |
0 |
0 |
T19 |
645 |
645 |
0 |
0 |
T20 |
1390 |
1390 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
106612844 |
106612844 |
0 |
0 |
T1 |
45110 |
45110 |
0 |
0 |
T2 |
30597 |
30597 |
0 |
0 |
T4 |
11154 |
11154 |
0 |
0 |
T5 |
19337 |
19337 |
0 |
0 |
T6 |
370 |
370 |
0 |
0 |
T7 |
515 |
515 |
0 |
0 |
T17 |
408 |
408 |
0 |
0 |
T18 |
386 |
386 |
0 |
0 |
T19 |
645 |
645 |
0 |
0 |
T20 |
1390 |
1390 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218609628 |
217584692 |
0 |
0 |
T1 |
90264 |
90224 |
0 |
0 |
T2 |
61229 |
61196 |
0 |
0 |
T4 |
35306 |
22307 |
0 |
0 |
T5 |
58857 |
38671 |
0 |
0 |
T6 |
725 |
658 |
0 |
0 |
T7 |
1062 |
994 |
0 |
0 |
T17 |
880 |
819 |
0 |
0 |
T18 |
790 |
771 |
0 |
0 |
T19 |
1316 |
1290 |
0 |
0 |
T20 |
2813 |
2780 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218609628 |
217584692 |
0 |
0 |
T1 |
90264 |
90224 |
0 |
0 |
T2 |
61229 |
61196 |
0 |
0 |
T4 |
35306 |
22307 |
0 |
0 |
T5 |
58857 |
38671 |
0 |
0 |
T6 |
725 |
658 |
0 |
0 |
T7 |
1062 |
994 |
0 |
0 |
T17 |
880 |
819 |
0 |
0 |
T18 |
790 |
771 |
0 |
0 |
T19 |
1316 |
1290 |
0 |
0 |
T20 |
2813 |
2780 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164904611 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
121184 |
121089 |
0 |
3 |
T4 |
9562 |
2162 |
0 |
3 |
T5 |
20844 |
7187 |
0 |
3 |
T6 |
1745 |
1486 |
0 |
3 |
T7 |
2169 |
1931 |
0 |
3 |
T17 |
1564 |
1373 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
1618 |
1499 |
0 |
3 |
T20 |
1464 |
1419 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164904611 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
121184 |
121089 |
0 |
3 |
T4 |
9562 |
2162 |
0 |
3 |
T5 |
20844 |
7187 |
0 |
3 |
T6 |
1745 |
1486 |
0 |
3 |
T7 |
2169 |
1931 |
0 |
3 |
T17 |
1564 |
1373 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
1618 |
1499 |
0 |
3 |
T20 |
1464 |
1419 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164904611 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
121184 |
121089 |
0 |
3 |
T4 |
9562 |
2162 |
0 |
3 |
T5 |
20844 |
7187 |
0 |
3 |
T6 |
1745 |
1486 |
0 |
3 |
T7 |
2169 |
1931 |
0 |
3 |
T17 |
1564 |
1373 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
1618 |
1499 |
0 |
3 |
T20 |
1464 |
1419 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164904611 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
121184 |
121089 |
0 |
3 |
T4 |
9562 |
2162 |
0 |
3 |
T5 |
20844 |
7187 |
0 |
3 |
T6 |
1745 |
1486 |
0 |
3 |
T7 |
2169 |
1931 |
0 |
3 |
T17 |
1564 |
1373 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
1618 |
1499 |
0 |
3 |
T20 |
1464 |
1419 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164904611 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
121184 |
121089 |
0 |
3 |
T4 |
9562 |
2162 |
0 |
3 |
T5 |
20844 |
7187 |
0 |
3 |
T6 |
1745 |
1486 |
0 |
3 |
T7 |
2169 |
1931 |
0 |
3 |
T17 |
1564 |
1373 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
1618 |
1499 |
0 |
3 |
T20 |
1464 |
1419 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164904611 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
121184 |
121089 |
0 |
3 |
T4 |
9562 |
2162 |
0 |
3 |
T5 |
20844 |
7187 |
0 |
3 |
T6 |
1745 |
1486 |
0 |
3 |
T7 |
2169 |
1931 |
0 |
3 |
T17 |
1564 |
1373 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
1618 |
1499 |
0 |
3 |
T20 |
1464 |
1419 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
164911917 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
121184 |
121092 |
0 |
0 |
T4 |
9562 |
2201 |
0 |
0 |
T5 |
20844 |
7229 |
0 |
0 |
T6 |
1745 |
1489 |
0 |
0 |
T7 |
2169 |
1934 |
0 |
0 |
T17 |
1564 |
1376 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
1618 |
1502 |
0 |
0 |
T20 |
1464 |
1422 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451621570 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
127558 |
127457 |
0 |
3 |
T4 |
73554 |
16889 |
0 |
3 |
T5 |
122618 |
42407 |
0 |
3 |
T6 |
1647 |
1375 |
0 |
3 |
T7 |
2213 |
1970 |
0 |
3 |
T17 |
1839 |
1596 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
2742 |
2541 |
0 |
3 |
T20 |
5860 |
5688 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
32263 |
0 |
0 |
T1 |
188046 |
1 |
0 |
0 |
T2 |
127558 |
1 |
0 |
0 |
T4 |
73554 |
13 |
0 |
0 |
T5 |
122618 |
14 |
0 |
0 |
T6 |
1647 |
16 |
0 |
0 |
T7 |
2213 |
13 |
0 |
0 |
T17 |
1839 |
15 |
0 |
0 |
T18 |
1647 |
7 |
0 |
0 |
T19 |
2742 |
3 |
0 |
0 |
T20 |
5860 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451621570 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
127558 |
127457 |
0 |
3 |
T4 |
73554 |
16889 |
0 |
3 |
T5 |
122618 |
42407 |
0 |
3 |
T6 |
1647 |
1375 |
0 |
3 |
T7 |
2213 |
1970 |
0 |
3 |
T17 |
1839 |
1596 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
2742 |
2541 |
0 |
3 |
T20 |
5860 |
5688 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
32310 |
0 |
0 |
T1 |
188046 |
1 |
0 |
0 |
T2 |
127558 |
1 |
0 |
0 |
T4 |
73554 |
13 |
0 |
0 |
T5 |
122618 |
14 |
0 |
0 |
T6 |
1647 |
13 |
0 |
0 |
T7 |
2213 |
11 |
0 |
0 |
T17 |
1839 |
15 |
0 |
0 |
T18 |
1647 |
4 |
0 |
0 |
T19 |
2742 |
3 |
0 |
0 |
T20 |
5860 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451621570 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
127558 |
127457 |
0 |
3 |
T4 |
73554 |
16889 |
0 |
3 |
T5 |
122618 |
42407 |
0 |
3 |
T6 |
1647 |
1375 |
0 |
3 |
T7 |
2213 |
1970 |
0 |
3 |
T17 |
1839 |
1596 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
2742 |
2541 |
0 |
3 |
T20 |
5860 |
5688 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
32191 |
0 |
0 |
T1 |
188046 |
1 |
0 |
0 |
T2 |
127558 |
1 |
0 |
0 |
T4 |
73554 |
13 |
0 |
0 |
T5 |
122618 |
14 |
0 |
0 |
T6 |
1647 |
15 |
0 |
0 |
T7 |
2213 |
11 |
0 |
0 |
T17 |
1839 |
12 |
0 |
0 |
T18 |
1647 |
1 |
0 |
0 |
T19 |
2742 |
3 |
0 |
0 |
T20 |
5860 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451621570 |
0 |
2412 |
T1 |
188046 |
187860 |
0 |
3 |
T2 |
127558 |
127457 |
0 |
3 |
T4 |
73554 |
16889 |
0 |
3 |
T5 |
122618 |
42407 |
0 |
3 |
T6 |
1647 |
1375 |
0 |
3 |
T7 |
2213 |
1970 |
0 |
3 |
T17 |
1839 |
1596 |
0 |
3 |
T18 |
1647 |
1575 |
0 |
3 |
T19 |
2742 |
2541 |
0 |
3 |
T20 |
5860 |
5688 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
32291 |
0 |
0 |
T1 |
188046 |
1 |
0 |
0 |
T2 |
127558 |
1 |
0 |
0 |
T4 |
73554 |
13 |
0 |
0 |
T5 |
122618 |
14 |
0 |
0 |
T6 |
1647 |
19 |
0 |
0 |
T7 |
2213 |
7 |
0 |
0 |
T17 |
1839 |
12 |
0 |
0 |
T18 |
1647 |
7 |
0 |
0 |
T19 |
2742 |
3 |
0 |
0 |
T20 |
5860 |
17 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
451628783 |
0 |
0 |
T1 |
188046 |
187863 |
0 |
0 |
T2 |
127558 |
127460 |
0 |
0 |
T4 |
73554 |
16928 |
0 |
0 |
T5 |
122618 |
42449 |
0 |
0 |
T6 |
1647 |
1378 |
0 |
0 |
T7 |
2213 |
1973 |
0 |
0 |
T17 |
1839 |
1599 |
0 |
0 |
T18 |
1647 |
1578 |
0 |
0 |
T19 |
2742 |
2544 |
0 |
0 |
T20 |
5860 |
5691 |
0 |
0 |