Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T4,T5,T22

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	167272387	164769701	0	0
AllClkBypReqTrue_A	167272387	139817	0	0
IoClkBypReqFalse_A	167272387	164688837	0	2412
IoClkBypReqTrue_A	167272387	215883	0	0
LcClkBypAckFalse_A	167272387	164779829	0	0
LcClkBypAckTrue_A	167272387	129689	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	164769701	0	0
T1	188046	187862	0	0
T2	121184	121091	0	0
T4	9562	2188	0	0
T5	20844	7215	0	0
T6	1745	1488	0	0
T7	2169	1838	0	0
T17	1564	1375	0	0
T18	1647	1577	0	0
T19	1618	1501	0	0
T20	1464	1421	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	139817	0	0
T2	121184	0	0	0
T3	0	326	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T7	2169	95	0	0
T10	0	1426	0	0
T11	0	61	0	0
T12	0	553	0	0
T13	0	303	0	0
T17	1564	0	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T21	2201	0	0	0
T22	9955	0	0	0
T29	0	181	0	0
T66	0	231	0	0
T107	0	423	0	0
T115	0	85	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	164688837	0	2412
T1	188046	187860	0	3
T2	121184	121089	0	3
T4	9562	2162	0	3
T5	20844	7187	0	3
T6	1745	1486	0	3
T7	2169	1931	0	3
T17	1564	1373	0	3
T18	1647	1575	0	3
T19	1618	1499	0	3
T20	1464	1419	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	215883	0	0
T3	86856	446	0	0
T10	263330	1862	0	0
T11	0	271	0	0
T12	0	869	0	0
T13	0	431	0	0
T25	13187	0	0	0
T26	83642	0	0	0
T27	17002	0	0	0
T28	2566	306	0	0
T29	1602	69	0	0
T36	716	0	0	0
T65	1463	0	0	0
T66	0	357	0	0
T71	0	31	0	0
T107	0	399	0	0
T116	3033	0	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	164779829	0	0
T1	188046	187862	0	0
T2	121184	121091	0	0
T4	9562	2188	0	0
T5	20844	7215	0	0
T6	1745	1488	0	0
T7	2169	1933	0	0
T17	1564	1375	0	0
T18	1647	1577	0	0
T19	1618	1501	0	0
T20	1464	1421	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	129689	0	0
T3	86856	297	0	0
T10	263330	1278	0	0
T11	0	142	0	0
T12	0	566	0	0
T13	0	326	0	0
T25	13187	0	0	0
T26	83642	0	0	0
T27	17002	0	0	0
T28	2566	53	0	0
T29	1602	65	0	0
T36	716	0	0	0
T65	1463	0	0	0
T66	0	234	0	0
T71	0	4	0	0
T107	0	270	0	0
T116	3033	0	0	0