Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1823329884	14993	0	0
TransStop_A	1823329884	7595	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1823329884	14993	0	0
T3	0	71	0	0
T10	0	185	0	0
T11	0	81	0	0
T18	3296	2	0	0
T19	5486	0	0	0
T20	23444	11	0	0
T21	35232	42	0	0
T22	39824	0	0	0
T28	10472	0	0	0
T29	64116	0	0	0
T35	8064	15	0	0
T36	11064	0	0	0
T67	0	17	0	0
T69	0	25	0	0
T72	5376	0	0	0
T73	13536	3	0	0
T116	6820	26	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1823329884	7595	0	0
T3	0	42	0	0
T10	0	92	0	0
T11	0	23	0	0
T12	0	23	0	0
T18	1648	1	0	0
T19	2743	0	0	0
T20	23444	5	0	0
T21	35232	19	0	0
T22	39824	0	0	0
T28	10472	0	0	0
T29	96174	0	0	0
T35	8064	9	0	0
T36	11064	0	0	0
T67	0	13	0	0
T69	0	14	0	0
T72	5376	0	0	0
T73	13536	2	0	0
T116	10230	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	455832471	3723	0	0
TransStop_A	455832471	1879	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832471	3723	0	0
T3	0	16	0	0
T10	0	41	0	0
T11	0	20	0	0
T18	1648	1	0	0
T19	2743	0	0	0
T20	5861	4	0	0
T21	8808	10	0	0
T22	9956	0	0	0
T28	2618	0	0	0
T35	2016	4	0	0
T36	2766	0	0	0
T67	0	3	0	0
T69	0	7	0	0
T72	1344	0	0	0
T73	3384	0	0	0
T116	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832471	1879	0	0
T3	0	10	0	0
T10	0	23	0	0
T11	0	5	0	0
T12	0	12	0	0
T20	5861	2	0	0
T21	8808	3	0	0
T22	9956	0	0	0
T28	2618	0	0	0
T29	32058	0	0	0
T35	2016	2	0	0
T36	2766	0	0	0
T67	0	3	0	0
T69	0	4	0	0
T72	1344	0	0	0
T73	3384	0	0	0
T116	3410	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	455832471	3765	0	0
TransStop_A	455832471	1937	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832471	3765	0	0
T3	0	20	0	0
T10	0	51	0	0
T11	0	24	0	0
T20	5861	4	0	0
T21	8808	10	0	0
T22	9956	0	0	0
T28	2618	0	0	0
T29	32058	0	0	0
T35	2016	6	0	0
T36	2766	0	0	0
T67	0	5	0	0
T69	0	6	0	0
T72	1344	0	0	0
T73	3384	1	0	0
T116	3410	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832471	1937	0	0
T3	0	12	0	0
T10	0	26	0	0
T11	0	7	0	0
T12	0	11	0	0
T20	5861	2	0	0
T21	8808	6	0	0
T22	9956	0	0	0
T28	2618	0	0	0
T29	32058	0	0	0
T35	2016	3	0	0
T36	2766	0	0	0
T67	0	3	0	0
T69	0	4	0	0
T72	1344	0	0	0
T73	3384	0	0	0
T116	3410	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	455832471	3745	0	0
TransStop_A	455832471	1897	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832471	3745	0	0
T3	0	20	0	0
T10	0	43	0	0
T11	0	22	0	0
T20	5861	3	0	0
T21	8808	9	0	0
T22	9956	0	0	0
T28	2618	0	0	0
T29	32058	0	0	0
T35	2016	1	0	0
T36	2766	0	0	0
T67	0	6	0	0
T69	0	7	0	0
T72	1344	0	0	0
T73	3384	1	0	0
T116	3410	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832471	1897	0	0
T3	0	10	0	0
T10	0	18	0	0
T11	0	6	0	0
T20	5861	1	0	0
T21	8808	5	0	0
T22	9956	0	0	0
T28	2618	0	0	0
T29	32058	0	0	0
T35	2016	1	0	0
T36	2766	0	0	0
T67	0	4	0	0
T69	0	4	0	0
T72	1344	0	0	0
T73	3384	1	0	0
T116	3410	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	455832471	3760	0	0
TransStop_A	455832471	1882	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832471	3760	0	0
T3	0	15	0	0
T10	0	50	0	0
T11	0	15	0	0
T18	1648	1	0	0
T19	2743	0	0	0
T20	5861	0	0	0
T21	8808	13	0	0
T22	9956	0	0	0
T28	2618	0	0	0
T35	2016	4	0	0
T36	2766	0	0	0
T67	0	3	0	0
T69	0	5	0	0
T72	1344	0	0	0
T73	3384	1	0	0
T116	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832471	1882	0	0
T3	0	10	0	0
T10	0	25	0	0
T11	0	5	0	0
T18	1648	1	0	0
T19	2743	0	0	0
T20	5861	0	0	0
T21	8808	5	0	0
T22	9956	0	0	0
T28	2618	0	0	0
T35	2016	3	0	0
T36	2766	0	0	0
T67	0	3	0	0
T69	0	2	0	0
T72	1344	0	0	0
T73	3384	1	0	0
T116	0	3	0	0