SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1608 | 1608 | 0 | 0 |
OutputsKnown_A | 334544774 | 329823834 | 0 | 0 |
gen_flops.OutputDelay_A | 334544774 | 329809222 | 0 | 4824 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1608 | 1608 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T17 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T19 | 2 | 2 | 0 | 0 |
T20 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 334544774 | 329823834 | 0 | 0 |
T1 | 376092 | 375726 | 0 | 0 |
T2 | 242368 | 242184 | 0 | 0 |
T4 | 19124 | 4402 | 0 | 0 |
T5 | 41688 | 14458 | 0 | 0 |
T6 | 3490 | 2978 | 0 | 0 |
T7 | 4338 | 3868 | 0 | 0 |
T17 | 3128 | 2752 | 0 | 0 |
T18 | 3294 | 3156 | 0 | 0 |
T19 | 3236 | 3004 | 0 | 0 |
T20 | 2928 | 2844 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 334544774 | 329809222 | 0 | 4824 |
T1 | 376092 | 375720 | 0 | 6 |
T2 | 242368 | 242178 | 0 | 6 |
T4 | 19124 | 4324 | 0 | 6 |
T5 | 41688 | 14374 | 0 | 6 |
T6 | 3490 | 2972 | 0 | 6 |
T7 | 4338 | 3862 | 0 | 6 |
T17 | 3128 | 2746 | 0 | 6 |
T18 | 3294 | 3150 | 0 | 6 |
T19 | 3236 | 2998 | 0 | 6 |
T20 | 2928 | 2838 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 804 | 804 | 0 | 0 |
OutputsKnown_A | 167272387 | 164911917 | 0 | 0 |
gen_flops.OutputDelay_A | 167272387 | 164904611 | 0 | 2412 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 804 | 804 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167272387 | 164911917 | 0 | 0 |
T1 | 188046 | 187863 | 0 | 0 |
T2 | 121184 | 121092 | 0 | 0 |
T4 | 9562 | 2201 | 0 | 0 |
T5 | 20844 | 7229 | 0 | 0 |
T6 | 1745 | 1489 | 0 | 0 |
T7 | 2169 | 1934 | 0 | 0 |
T17 | 1564 | 1376 | 0 | 0 |
T18 | 1647 | 1578 | 0 | 0 |
T19 | 1618 | 1502 | 0 | 0 |
T20 | 1464 | 1422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167272387 | 164904611 | 0 | 2412 |
T1 | 188046 | 187860 | 0 | 3 |
T2 | 121184 | 121089 | 0 | 3 |
T4 | 9562 | 2162 | 0 | 3 |
T5 | 20844 | 7187 | 0 | 3 |
T6 | 1745 | 1486 | 0 | 3 |
T7 | 2169 | 1931 | 0 | 3 |
T17 | 1564 | 1373 | 0 | 3 |
T18 | 1647 | 1575 | 0 | 3 |
T19 | 1618 | 1499 | 0 | 3 |
T20 | 1464 | 1419 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 804 | 804 | 0 | 0 |
OutputsKnown_A | 167272387 | 164911917 | 0 | 0 |
gen_flops.OutputDelay_A | 167272387 | 164904611 | 0 | 2412 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 804 | 804 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167272387 | 164911917 | 0 | 0 |
T1 | 188046 | 187863 | 0 | 0 |
T2 | 121184 | 121092 | 0 | 0 |
T4 | 9562 | 2201 | 0 | 0 |
T5 | 20844 | 7229 | 0 | 0 |
T6 | 1745 | 1489 | 0 | 0 |
T7 | 2169 | 1934 | 0 | 0 |
T17 | 1564 | 1376 | 0 | 0 |
T18 | 1647 | 1578 | 0 | 0 |
T19 | 1618 | 1502 | 0 | 0 |
T20 | 1464 | 1422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167272387 | 164904611 | 0 | 2412 |
T1 | 188046 | 187860 | 0 | 3 |
T2 | 121184 | 121089 | 0 | 3 |
T4 | 9562 | 2162 | 0 | 3 |
T5 | 20844 | 7187 | 0 | 3 |
T6 | 1745 | 1486 | 0 | 3 |
T7 | 2169 | 1931 | 0 | 3 |
T17 | 1564 | 1373 | 0 | 3 |
T18 | 1647 | 1575 | 0 | 3 |
T19 | 1618 | 1499 | 0 | 3 |
T20 | 1464 | 1419 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |