Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	167272387	18958921	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	18958921	0	60
T1	188046	49051	0	1
T2	121184	23915	0	1
T3	0	10682	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T7	2169	0	0	0
T10	0	118950	0	0
T11	0	73172	0	1
T12	0	339435	0	0
T13	0	23860	0	1
T14	0	10892	0	1
T15	0	13741	0	1
T16	0	55354	0	0
T17	1564	0	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T21	2201	0	0	0
T24	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1
T119	0	0	0	1