Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	168244631	5492981	0	0
clk_enables_rd_A	168244631	46795	0	0
clk_hints_rd_A	168244631	42340	0	0
extclk_ctrl_rd_A	168244631	52512	0	0
extclk_ctrl_regwen_rd_A	168244631	40613	0	0
jitter_enable_rd_A	168244631	57290	0	0
jitter_regwen_rd_A	168244631	45140	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168244631	5492981	0	0
T10	263330	84521	0	0
T11	248970	0	0	0
T12	0	66753	0	0
T16	0	12776	0	0
T27	17002	0	0	0
T58	0	142682	0	0
T59	0	138172	0	0
T60	0	44064	0	0
T61	0	48078	0	0
T62	0	92850	0	0
T63	0	57570	0	0
T64	0	86634	0	0
T65	1463	0	0	0
T66	2495	0	0	0
T67	1632	0	0	0
T68	5207	0	0	0
T69	2110	0	0	0
T70	1354	0	0	0
T71	1322	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168244631	46795	0	0
T10	263330	1809	0	0
T11	248970	0	0	0
T13	0	10	0	0
T16	0	588	0	0
T27	17002	0	0	0
T32	0	4221	0	0
T65	1463	0	0	0
T66	2495	0	0	0
T67	1632	0	0	0
T68	5207	0	0	0
T69	2110	0	0	0
T70	1354	0	0	0
T71	1322	0	0	0
T77	0	6	0	0
T138	0	13	0	0
T139	0	1	0	0
T140	0	1728	0	0
T141	0	4	0	0
T142	0	645	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168244631	42340	0	0
T10	263330	1482	0	0
T11	248970	0	0	0
T13	0	2	0	0
T16	0	404	0	0
T27	17002	0	0	0
T32	0	4076	0	0
T65	1463	0	0	0
T66	2495	0	0	0
T67	1632	0	0	0
T68	5207	0	0	0
T69	2110	0	0	0
T70	1354	0	0	0
T71	1322	0	0	0
T77	0	7	0	0
T138	0	11	0	0
T139	0	1	0	0
T140	0	1493	0	0
T141	0	5	0	0
T142	0	582	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168244631	52512	0	0
T2	121184	0	0	0
T4	9562	0	0	0
T5	20844	82	0	0
T7	2169	36	0	0
T10	0	1971	0	0
T11	0	37	0	0
T13	0	34	0	0
T17	1564	0	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T21	2201	0	0	0
T22	9955	0	0	0
T29	0	6	0	0
T68	0	35	0	0
T77	0	36	0	0
T90	0	27	0	0
T94	0	53	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168244631	40613	0	0
T2	121184	0	0	0
T5	20844	47	0	0
T10	0	1468	0	0
T16	0	402	0	0
T17	1564	0	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T21	2201	0	0	0
T22	9955	0	0	0
T32	0	3966	0	0
T35	1934	0	0	0
T68	0	21	0	0
T72	1343	0	0	0
T140	0	1466	0	0
T142	0	471	0	0
T143	0	70	0	0
T144	0	3579	0	0
T145	0	65	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168244631	57290	0	0
T10	263330	1937	0	0
T11	248970	0	0	0
T13	0	447	0	0
T16	0	1355	0	0
T27	17002	0	0	0
T32	0	5241	0	0
T65	1463	0	0	0
T66	2495	0	0	0
T67	1632	0	0	0
T68	5207	0	0	0
T69	2110	0	0	0
T70	1354	0	0	0
T71	1322	0	0	0
T77	0	232	0	0
T138	0	267	0	0
T139	0	223	0	0
T140	0	2306	0	0
T141	0	117	0	0
T142	0	564	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168244631	45140	0	0
T10	263330	1929	0	0
T11	248970	0	0	0
T16	0	418	0	0
T27	17002	0	0	0
T32	0	4334	0	0
T65	1463	0	0	0
T66	2495	0	0	0
T67	1632	0	0	0
T68	5207	0	0	0
T69	2110	0	0	0
T70	1354	0	0	0
T71	1322	0	0	0
T140	0	1691	0	0
T142	0	563	0	0
T144	0	3789	0	0
T146	0	3693	0	0
T147	0	3463	0	0
T148	0	2495	0	0
T149	0	6088	0	0