Line Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 3 | 50.00 |
Logical | 6 | 3 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T6,T1,T7 |
1 | 1 | Covered | T6,T1,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T6,T1,T7 |
Branch Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Module :
prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
17671456 |
0 |
0 |
T1 |
2474619 |
396 |
0 |
0 |
T2 |
1614869 |
267 |
0 |
0 |
T3 |
0 |
95 |
0 |
0 |
T4 |
308553 |
92 |
0 |
0 |
T5 |
565632 |
138 |
0 |
0 |
T6 |
5096 |
96 |
0 |
0 |
T7 |
28634 |
123 |
0 |
0 |
T10 |
0 |
361 |
0 |
0 |
T11 |
0 |
35 |
0 |
0 |
T12 |
0 |
158 |
0 |
0 |
T13 |
0 |
83 |
0 |
0 |
T14 |
0 |
30 |
0 |
0 |
T15 |
0 |
25 |
0 |
0 |
T16 |
0 |
196 |
0 |
0 |
T17 |
21338 |
103 |
0 |
0 |
T18 |
21645 |
100 |
0 |
0 |
T19 |
24805 |
158 |
0 |
0 |
T20 |
33109 |
348 |
0 |
0 |
T21 |
22010 |
0 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T23 |
0 |
36 |
0 |
0 |
T24 |
0 |
3 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
131419 |
0 |
0 |
T1 |
1188318 |
186 |
0 |
0 |
T2 |
806058 |
137 |
0 |
0 |
T3 |
0 |
353 |
0 |
0 |
T4 |
425866 |
108 |
0 |
0 |
T5 |
714384 |
122 |
0 |
0 |
T7 |
13888 |
0 |
0 |
0 |
T10 |
0 |
1332 |
0 |
0 |
T11 |
0 |
42 |
0 |
0 |
T12 |
0 |
195 |
0 |
0 |
T13 |
0 |
100 |
0 |
0 |
T14 |
0 |
34 |
0 |
0 |
T15 |
0 |
29 |
0 |
0 |
T16 |
0 |
239 |
0 |
0 |
T17 |
11396 |
0 |
0 |
0 |
T18 |
10350 |
0 |
0 |
0 |
T19 |
17250 |
0 |
0 |
0 |
T20 |
36938 |
0 |
0 |
0 |
T21 |
55560 |
0 |
0 |
0 |
T22 |
0 |
9 |
0 |
0 |
T23 |
0 |
36 |
0 |
0 |
T24 |
0 |
3 |
0 |
0 |
T25 |
0 |
40 |
0 |
0 |
T26 |
0 |
70 |
0 |
0 |
T27 |
0 |
90 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T6,T1,T7 |
1 | 1 | Covered | T6,T1,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427507042 |
3538020 |
0 |
0 |
T1 |
180519 |
85 |
0 |
0 |
T2 |
122452 |
57 |
0 |
0 |
T4 |
70610 |
17 |
0 |
0 |
T5 |
117709 |
28 |
0 |
0 |
T6 |
1614 |
25 |
0 |
0 |
T7 |
2124 |
31 |
0 |
0 |
T17 |
1754 |
26 |
0 |
0 |
T18 |
1581 |
25 |
0 |
0 |
T19 |
2632 |
40 |
0 |
0 |
T20 |
5626 |
88 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15971373 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T6,T1,T7 |
1 | 1 | Covered | T6,T1,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
213227110 |
3537872 |
0 |
0 |
T1 |
90220 |
85 |
0 |
0 |
T2 |
61193 |
57 |
0 |
0 |
T4 |
22309 |
17 |
0 |
0 |
T5 |
38671 |
28 |
0 |
0 |
T6 |
740 |
24 |
0 |
0 |
T7 |
1030 |
31 |
0 |
0 |
T17 |
817 |
26 |
0 |
0 |
T18 |
771 |
25 |
0 |
0 |
T19 |
1290 |
40 |
0 |
0 |
T20 |
2780 |
88 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15971373 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T6,T1,T7 |
1 | 1 | Covered | T6,T1,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
106612844 |
3374838 |
0 |
0 |
T1 |
45110 |
85 |
0 |
0 |
T2 |
30597 |
57 |
0 |
0 |
T4 |
11154 |
17 |
0 |
0 |
T5 |
19337 |
28 |
0 |
0 |
T6 |
370 |
23 |
0 |
0 |
T7 |
515 |
30 |
0 |
0 |
T17 |
408 |
25 |
0 |
0 |
T18 |
386 |
25 |
0 |
0 |
T19 |
645 |
38 |
0 |
0 |
T20 |
1390 |
84 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15971373 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T6,T1,T7 |
1 | 1 | Covered | T6,T1,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
3542067 |
0 |
0 |
T1 |
188046 |
85 |
0 |
0 |
T2 |
127558 |
57 |
0 |
0 |
T4 |
73554 |
17 |
0 |
0 |
T5 |
122618 |
28 |
0 |
0 |
T6 |
1647 |
24 |
0 |
0 |
T7 |
2213 |
31 |
0 |
0 |
T17 |
1839 |
26 |
0 |
0 |
T18 |
1647 |
25 |
0 |
0 |
T19 |
2742 |
40 |
0 |
0 |
T20 |
5860 |
88 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15971373 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T6,T1,T7 |
1 | 1 | Covered | T6,T1,T7 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T6,T1,T7 |
EVEN |
0 |
- |
Covered |
T6,T1,T7 |
ODD |
- |
1 |
Covered |
T6,T1,T7 |
ODD |
- |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218609628 |
3541797 |
0 |
0 |
T1 |
90264 |
85 |
0 |
0 |
T2 |
61229 |
57 |
0 |
0 |
T4 |
35306 |
17 |
0 |
0 |
T5 |
58857 |
28 |
0 |
0 |
T6 |
725 |
22 |
0 |
0 |
T7 |
1062 |
31 |
0 |
0 |
T17 |
880 |
27 |
0 |
0 |
T18 |
790 |
25 |
0 |
0 |
T19 |
1316 |
40 |
0 |
0 |
T20 |
2813 |
88 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15971373 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
168244631 |
24731 |
0 |
0 |
T1 |
188046 |
36 |
0 |
0 |
T2 |
121184 |
24 |
0 |
0 |
T3 |
0 |
68 |
0 |
0 |
T4 |
9562 |
24 |
0 |
0 |
T5 |
20844 |
26 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
252 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429934169 |
23679 |
0 |
0 |
T1 |
180519 |
32 |
0 |
0 |
T2 |
122452 |
22 |
0 |
0 |
T3 |
0 |
64 |
0 |
0 |
T4 |
70610 |
24 |
0 |
0 |
T5 |
117709 |
26 |
0 |
0 |
T7 |
2124 |
0 |
0 |
0 |
T10 |
0 |
239 |
0 |
0 |
T17 |
1754 |
0 |
0 |
0 |
T18 |
1581 |
0 |
0 |
0 |
T19 |
2632 |
0 |
0 |
0 |
T20 |
5626 |
0 |
0 |
0 |
T21 |
8455 |
0 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
168244631 |
24731 |
0 |
0 |
T1 |
188046 |
36 |
0 |
0 |
T2 |
121184 |
24 |
0 |
0 |
T3 |
0 |
68 |
0 |
0 |
T4 |
9562 |
24 |
0 |
0 |
T5 |
20844 |
26 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
252 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
214393642 |
23676 |
0 |
0 |
T1 |
90220 |
32 |
0 |
0 |
T2 |
61193 |
22 |
0 |
0 |
T3 |
0 |
64 |
0 |
0 |
T4 |
22309 |
24 |
0 |
0 |
T5 |
38671 |
26 |
0 |
0 |
T7 |
1030 |
0 |
0 |
0 |
T10 |
0 |
239 |
0 |
0 |
T17 |
817 |
0 |
0 |
0 |
T18 |
771 |
0 |
0 |
0 |
T19 |
1290 |
0 |
0 |
0 |
T20 |
2780 |
0 |
0 |
0 |
T21 |
4194 |
0 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
168244631 |
24731 |
0 |
0 |
T1 |
188046 |
36 |
0 |
0 |
T2 |
121184 |
24 |
0 |
0 |
T3 |
0 |
68 |
0 |
0 |
T4 |
9562 |
24 |
0 |
0 |
T5 |
20844 |
26 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
252 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
107196086 |
23633 |
0 |
0 |
T1 |
45110 |
32 |
0 |
0 |
T2 |
30597 |
22 |
0 |
0 |
T3 |
0 |
64 |
0 |
0 |
T4 |
11154 |
24 |
0 |
0 |
T5 |
19337 |
26 |
0 |
0 |
T7 |
515 |
0 |
0 |
0 |
T10 |
0 |
239 |
0 |
0 |
T17 |
408 |
0 |
0 |
0 |
T18 |
386 |
0 |
0 |
0 |
T19 |
645 |
0 |
0 |
0 |
T20 |
1390 |
0 |
0 |
0 |
T21 |
2097 |
0 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T4,T5 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
168244631 |
24731 |
0 |
0 |
T1 |
188046 |
36 |
0 |
0 |
T2 |
121184 |
24 |
0 |
0 |
T3 |
0 |
68 |
0 |
0 |
T4 |
9562 |
24 |
0 |
0 |
T5 |
20844 |
26 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
252 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
458360378 |
23679 |
0 |
0 |
T1 |
188046 |
32 |
0 |
0 |
T2 |
127558 |
22 |
0 |
0 |
T3 |
0 |
64 |
0 |
0 |
T4 |
73554 |
24 |
0 |
0 |
T5 |
122618 |
26 |
0 |
0 |
T7 |
2213 |
0 |
0 |
0 |
T10 |
0 |
239 |
0 |
0 |
T17 |
1839 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
2742 |
0 |
0 |
0 |
T20 |
5860 |
0 |
0 |
0 |
T21 |
8807 |
0 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T5,T2 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T4,T5 |
EVEN |
0 |
- |
Covered |
T1,T4,T5 |
ODD |
- |
1 |
Covered |
T1,T5,T2 |
ODD |
- |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
168244631 |
24299 |
0 |
0 |
T1 |
188046 |
36 |
0 |
0 |
T2 |
121184 |
24 |
0 |
0 |
T3 |
0 |
68 |
0 |
0 |
T4 |
9562 |
12 |
0 |
0 |
T5 |
20844 |
21 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
252 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219823213 |
23113 |
0 |
0 |
T1 |
90264 |
32 |
0 |
0 |
T2 |
61229 |
22 |
0 |
0 |
T3 |
0 |
64 |
0 |
0 |
T4 |
35306 |
12 |
0 |
0 |
T5 |
58857 |
18 |
0 |
0 |
T7 |
1062 |
0 |
0 |
0 |
T10 |
0 |
239 |
0 |
0 |
T17 |
880 |
0 |
0 |
0 |
T18 |
790 |
0 |
0 |
0 |
T19 |
1316 |
0 |
0 |
0 |
T20 |
2813 |
0 |
0 |
0 |
T21 |
4227 |
0 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
14 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T10 |
1 | 1 | Covered | T1,T2,T10 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T10 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T10 |
EVEN |
0 |
- |
Covered |
T1,T2,T10 |
ODD |
- |
1 |
Covered |
T1,T2,T10 |
ODD |
- |
0 |
Covered |
T1,T2,T10 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T10 |
EVEN |
0 |
- |
Covered |
T1,T2,T10 |
ODD |
- |
1 |
Covered |
T1,T2,T10 |
ODD |
- |
0 |
Covered |
T1,T2,T10 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
2812 |
0 |
0 |
T1 |
188046 |
4 |
0 |
0 |
T2 |
121184 |
3 |
0 |
0 |
T4 |
9562 |
0 |
0 |
0 |
T5 |
20844 |
0 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
27 |
0 |
0 |
T11 |
0 |
8 |
0 |
0 |
T12 |
0 |
46 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
5 |
0 |
0 |
T15 |
0 |
8 |
0 |
0 |
T16 |
0 |
97 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T24 |
0 |
3 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427507042 |
2812 |
0 |
0 |
T1 |
180519 |
4 |
0 |
0 |
T2 |
122452 |
3 |
0 |
0 |
T4 |
70610 |
0 |
0 |
0 |
T5 |
117709 |
0 |
0 |
0 |
T7 |
2124 |
0 |
0 |
0 |
T10 |
0 |
27 |
0 |
0 |
T11 |
0 |
8 |
0 |
0 |
T12 |
0 |
46 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T14 |
0 |
5 |
0 |
0 |
T15 |
0 |
8 |
0 |
0 |
T16 |
0 |
97 |
0 |
0 |
T17 |
1754 |
0 |
0 |
0 |
T18 |
1581 |
0 |
0 |
0 |
T19 |
2632 |
0 |
0 |
0 |
T20 |
5626 |
0 |
0 |
0 |
T21 |
8455 |
0 |
0 |
0 |
T24 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
2899 |
0 |
0 |
T1 |
188046 |
10 |
0 |
0 |
T2 |
121184 |
6 |
0 |
0 |
T3 |
0 |
4 |
0 |
0 |
T4 |
9562 |
0 |
0 |
0 |
T5 |
20844 |
0 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
37 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T12 |
0 |
50 |
0 |
0 |
T13 |
0 |
25 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T16 |
0 |
23 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T23 |
0 |
15 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
213227110 |
2899 |
0 |
0 |
T1 |
90220 |
10 |
0 |
0 |
T2 |
61193 |
6 |
0 |
0 |
T3 |
0 |
4 |
0 |
0 |
T4 |
22309 |
0 |
0 |
0 |
T5 |
38671 |
0 |
0 |
0 |
T7 |
1030 |
0 |
0 |
0 |
T10 |
0 |
37 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T12 |
0 |
50 |
0 |
0 |
T13 |
0 |
25 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T16 |
0 |
23 |
0 |
0 |
T17 |
817 |
0 |
0 |
0 |
T18 |
771 |
0 |
0 |
0 |
T19 |
1290 |
0 |
0 |
0 |
T20 |
2780 |
0 |
0 |
0 |
T21 |
4194 |
0 |
0 |
0 |
T23 |
0 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T10 |
1 | 1 | Covered | T1,T3,T10 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T3,T10 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T3,T10 |
EVEN |
0 |
- |
Covered |
T1,T3,T10 |
ODD |
- |
1 |
Covered |
T1,T3,T10 |
ODD |
- |
0 |
Covered |
T1,T3,T10 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T3,T10 |
EVEN |
0 |
- |
Covered |
T1,T3,T10 |
ODD |
- |
1 |
Covered |
T1,T3,T10 |
ODD |
- |
0 |
Covered |
T1,T3,T10 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
2737 |
0 |
0 |
T1 |
188046 |
3 |
0 |
0 |
T2 |
121184 |
0 |
0 |
0 |
T3 |
0 |
16 |
0 |
0 |
T4 |
9562 |
0 |
0 |
0 |
T5 |
20844 |
0 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
23 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
34 |
0 |
0 |
T13 |
0 |
28 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
7 |
0 |
0 |
T16 |
0 |
46 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T23 |
0 |
11 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
106612844 |
2737 |
0 |
0 |
T1 |
45110 |
3 |
0 |
0 |
T2 |
30597 |
0 |
0 |
0 |
T3 |
0 |
16 |
0 |
0 |
T4 |
11154 |
0 |
0 |
0 |
T5 |
19337 |
0 |
0 |
0 |
T7 |
515 |
0 |
0 |
0 |
T10 |
0 |
23 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
34 |
0 |
0 |
T13 |
0 |
28 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
7 |
0 |
0 |
T16 |
0 |
46 |
0 |
0 |
T17 |
408 |
0 |
0 |
0 |
T18 |
386 |
0 |
0 |
0 |
T19 |
645 |
0 |
0 |
0 |
T20 |
1390 |
0 |
0 |
0 |
T21 |
2097 |
0 |
0 |
0 |
T23 |
0 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_main_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
2569 |
0 |
0 |
T1 |
188046 |
3 |
0 |
0 |
T2 |
121184 |
6 |
0 |
0 |
T3 |
0 |
7 |
0 |
0 |
T4 |
9562 |
0 |
0 |
0 |
T5 |
20844 |
0 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
22 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
28 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T15 |
0 |
10 |
0 |
0 |
T16 |
0 |
30 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
455832013 |
2569 |
0 |
0 |
T1 |
188046 |
3 |
0 |
0 |
T2 |
127558 |
6 |
0 |
0 |
T3 |
0 |
7 |
0 |
0 |
T4 |
73554 |
0 |
0 |
0 |
T5 |
122618 |
0 |
0 |
0 |
T7 |
2213 |
0 |
0 |
0 |
T10 |
0 |
22 |
0 |
0 |
T11 |
0 |
10 |
0 |
0 |
T12 |
0 |
28 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T15 |
0 |
10 |
0 |
0 |
T16 |
0 |
30 |
0 |
0 |
T17 |
1839 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
2742 |
0 |
0 |
0 |
T20 |
5860 |
0 |
0 |
0 |
T21 |
8807 |
0 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167272387 |
2622 |
0 |
0 |
T1 |
188046 |
6 |
0 |
0 |
T2 |
121184 |
12 |
0 |
0 |
T3 |
0 |
6 |
0 |
0 |
T4 |
9562 |
0 |
0 |
0 |
T5 |
20844 |
0 |
0 |
0 |
T7 |
2169 |
0 |
0 |
0 |
T10 |
0 |
28 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T12 |
0 |
37 |
0 |
0 |
T13 |
0 |
17 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T15 |
0 |
4 |
0 |
0 |
T16 |
0 |
43 |
0 |
0 |
T17 |
1564 |
0 |
0 |
0 |
T18 |
1647 |
0 |
0 |
0 |
T19 |
1618 |
0 |
0 |
0 |
T20 |
1464 |
0 |
0 |
0 |
T21 |
2201 |
0 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218609628 |
2622 |
0 |
0 |
T1 |
90264 |
6 |
0 |
0 |
T2 |
61229 |
12 |
0 |
0 |
T3 |
0 |
6 |
0 |
0 |
T4 |
35306 |
0 |
0 |
0 |
T5 |
58857 |
0 |
0 |
0 |
T7 |
1062 |
0 |
0 |
0 |
T10 |
0 |
28 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T12 |
0 |
37 |
0 |
0 |
T13 |
0 |
17 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T15 |
0 |
4 |
0 |
0 |
T16 |
0 |
43 |
0 |
0 |
T17 |
880 |
0 |
0 |
0 |
T18 |
790 |
0 |
0 |
0 |
T19 |
1316 |
0 |
0 |
0 |
T20 |
2813 |
0 |
0 |
0 |
T21 |
4227 |
0 |
0 |
0 |