Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T18
1	0	Covered	T7,T28,T3
1	1	Covered	T7,T28,T29

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	427507459	4566	0	0
g_div2.Div2Whole_A	427507459	5515	0	0
g_div4.Div4Stepped_A	213227515	4475	0	0
g_div4.Div4Whole_A	213227515	5153	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507459	4566	0	0
T2	122452	0	0	0
T3	0	10	0	0
T4	70610	0	0	0
T5	117710	0	0	0
T7	2124	2	0	0
T10	0	30	0	0
T11	0	4	0	0
T12	0	28	0	0
T13	0	8	0	0
T17	1754	0	0	0
T18	1582	0	0	0
T19	2633	0	0	0
T20	5626	0	0	0
T21	8456	0	0	0
T22	9558	0	0	0
T28	0	1	0	0
T29	0	8	0	0
T66	0	8	0	0
T107	0	11	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507459	5515	0	0
T2	122452	0	0	0
T3	0	10	0	0
T4	70610	0	0	0
T5	117710	0	0	0
T7	2124	3	0	0
T10	0	36	0	0
T11	0	7	0	0
T12	0	30	0	0
T17	1754	0	0	0
T18	1582	0	0	0
T19	2633	0	0	0
T20	5626	0	0	0
T21	8456	0	0	0
T22	9558	0	0	0
T28	0	6	0	0
T29	0	8	0	0
T66	0	13	0	0
T71	0	1	0	0
T107	0	11	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227515	4475	0	0
T2	61194	0	0	0
T3	0	10	0	0
T4	22309	0	0	0
T5	38671	0	0	0
T7	1031	2	0	0
T10	0	30	0	0
T11	0	4	0	0
T12	0	27	0	0
T13	0	8	0	0
T17	817	0	0	0
T18	772	0	0	0
T19	1291	0	0	0
T20	2781	0	0	0
T21	4195	0	0	0
T22	2600	0	0	0
T28	0	1	0	0
T29	0	8	0	0
T66	0	8	0	0
T107	0	11	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227515	5153	0	0
T2	61194	0	0	0
T3	0	10	0	0
T4	22309	0	0	0
T5	38671	0	0	0
T7	1031	3	0	0
T10	0	36	0	0
T11	0	5	0	0
T12	0	30	0	0
T17	817	0	0	0
T18	772	0	0	0
T19	1291	0	0	0
T20	2781	0	0	0
T21	4195	0	0	0
T22	2600	0	0	0
T28	0	4	0	0
T29	0	8	0	0
T66	0	9	0	0
T71	0	1	0	0
T107	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T18
1	0	Covered	T7,T28,T3
1	1	Covered	T7,T28,T29

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	427507459	4566	0	0
g_div2.Div2Whole_A	427507459	5515	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507459	4566	0	0
T2	122452	0	0	0
T3	0	10	0	0
T4	70610	0	0	0
T5	117710	0	0	0
T7	2124	2	0	0
T10	0	30	0	0
T11	0	4	0	0
T12	0	28	0	0
T13	0	8	0	0
T17	1754	0	0	0
T18	1582	0	0	0
T19	2633	0	0	0
T20	5626	0	0	0
T21	8456	0	0	0
T22	9558	0	0	0
T28	0	1	0	0
T29	0	8	0	0
T66	0	8	0	0
T107	0	11	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507459	5515	0	0
T2	122452	0	0	0
T3	0	10	0	0
T4	70610	0	0	0
T5	117710	0	0	0
T7	2124	3	0	0
T10	0	36	0	0
T11	0	7	0	0
T12	0	30	0	0
T17	1754	0	0	0
T18	1582	0	0	0
T19	2633	0	0	0
T20	5626	0	0	0
T21	8456	0	0	0
T22	9558	0	0	0
T28	0	6	0	0
T29	0	8	0	0
T66	0	13	0	0
T71	0	1	0	0
T107	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T18
1	0	Covered	T7,T28,T3
1	1	Covered	T7,T28,T29

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	213227515	4475	0	0
g_div4.Div4Whole_A	213227515	5153	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227515	4475	0	0
T2	61194	0	0	0
T3	0	10	0	0
T4	22309	0	0	0
T5	38671	0	0	0
T7	1031	2	0	0
T10	0	30	0	0
T11	0	4	0	0
T12	0	27	0	0
T13	0	8	0	0
T17	817	0	0	0
T18	772	0	0	0
T19	1291	0	0	0
T20	2781	0	0	0
T21	4195	0	0	0
T22	2600	0	0	0
T28	0	1	0	0
T29	0	8	0	0
T66	0	8	0	0
T107	0	11	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227515	5153	0	0
T2	61194	0	0	0
T3	0	10	0	0
T4	22309	0	0	0
T5	38671	0	0	0
T7	1031	3	0	0
T10	0	36	0	0
T11	0	5	0	0
T12	0	30	0	0
T17	817	0	0	0
T18	772	0	0	0
T19	1291	0	0	0
T20	2781	0	0	0
T21	4195	0	0	0
T22	2600	0	0	0
T28	0	4	0	0
T29	0	8	0	0
T66	0	9	0	0
T71	0	1	0	0
T107	0	10	0	0