Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	501817161	464	0	0
StatusRise_A	501817161	464	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501817161	464	0	0
T1	564138	0	0	0
T2	363552	0	0	0
T4	28686	0	0	0
T5	62532	0	0	0
T6	5235	15	0	0
T7	6507	0	0	0
T17	4692	13	0	0
T18	4941	0	0	0
T19	4854	0	0	0
T20	4392	0	0	0
T36	0	5	0	0
T44	0	6	0	0
T89	0	6	0	0
T91	0	7	0	0
T93	0	12	0	0
T150	0	11	0	0
T151	0	3	0	0
T152	0	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501817161	464	0	0
T1	564138	0	0	0
T2	363552	0	0	0
T4	28686	0	0	0
T5	62532	0	0	0
T6	5235	15	0	0
T7	6507	0	0	0
T17	4692	13	0	0
T18	4941	0	0	0
T19	4854	0	0	0
T20	4392	0	0	0
T36	0	5	0	0
T44	0	6	0	0
T89	0	6	0	0
T91	0	7	0	0
T93	0	12	0	0
T150	0	11	0	0
T151	0	3	0	0
T152	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	167272387	143	0	0
StatusRise_A	167272387	143	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	143	0	0
T1	188046	0	0	0
T2	121184	0	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T6	1745	4	0	0
T7	2169	0	0	0
T17	1564	5	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T36	0	1	0	0
T44	0	3	0	0
T89	0	1	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	143	0	0
T1	188046	0	0	0
T2	121184	0	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T6	1745	4	0	0
T7	2169	0	0	0
T17	1564	5	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T36	0	1	0	0
T44	0	3	0	0
T89	0	1	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	167272387	156	0	0
StatusRise_A	167272387	156	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	156	0	0
T1	188046	0	0	0
T2	121184	0	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T6	1745	7	0	0
T7	2169	0	0	0
T17	1564	3	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	156	0	0
T1	188046	0	0	0
T2	121184	0	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T6	1745	7	0	0
T7	2169	0	0	0
T17	1564	3	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	167272387	165	0	0
StatusRise_A	167272387	165	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	165	0	0
T1	188046	0	0	0
T2	121184	0	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T6	1745	4	0	0
T7	2169	0	0	0
T17	1564	5	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T36	0	2	0	0
T44	0	1	0	0
T89	0	2	0	0
T91	0	3	0	0
T93	0	6	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167272387	165	0	0
T1	188046	0	0	0
T2	121184	0	0	0
T4	9562	0	0	0
T5	20844	0	0	0
T6	1745	4	0	0
T7	2169	0	0	0
T17	1564	5	0	0
T18	1647	0	0	0
T19	1618	0	0	0
T20	1464	0	0	0
T36	0	2	0	0
T44	0	1	0	0
T89	0	2	0	0
T91	0	3	0	0
T93	0	6	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	3	0	0