Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47825	0	0
CgEnOn_A	2147483647	38220	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47825	0	0
T1	2030722	3	0	0
T2	1377484	3	0	0
T4	742390	39	0	0
T5	1243530	42	0	0
T6	17520	63	0	0
T7	23770	3	0	0
T10	0	46	0	0
T17	19568	32	0	0
T18	17710	4	0	0
T19	29508	3	0	0
T20	63158	7	0	0
T21	0	10	0	0
T35	0	4	0	0
T36	0	11	0	0
T44	0	10	0	0
T89	0	15	0	0
T91	0	10	0	0
T93	0	15	0	0
T116	0	6	0	0
T150	0	15	0	0
T151	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38220	0	0
T1	2030722	0	0	0
T2	1377484	0	0	0
T3	0	142	0	0
T4	742390	0	0	0
T5	1243530	0	0	0
T6	17520	64	0	0
T7	23770	0	0	0
T10	0	401	0	0
T12	0	228	0	0
T17	19568	34	0	0
T18	17710	1	0	0
T19	29508	0	0	0
T20	63158	8	0	0
T21	0	20	0	0
T35	0	10	0	0
T36	0	18	0	0
T44	0	10	0	0
T65	0	29	0	0
T70	0	12	0	0
T72	0	19	0	0
T73	0	1	0	0
T89	0	15	0	0
T91	0	10	0	0
T93	0	15	0	0
T116	0	13	0	0
T150	0	24	0	0
T151	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	213227110	161	0	0
CgEnOn_A	213227110	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227110	161	0	0
T1	90220	0	0	0
T2	61193	0	0	0
T4	22309	0	0	0
T5	38671	0	0	0
T6	740	7	0	0
T7	1030	0	0	0
T10	0	1	0	0
T17	817	3	0	0
T18	771	0	0	0
T19	1290	0	0	0
T20	2780	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227110	161	0	0
T1	90220	0	0	0
T2	61193	0	0	0
T4	22309	0	0	0
T5	38671	0	0	0
T6	740	7	0	0
T7	1030	0	0	0
T10	0	1	0	0
T17	817	3	0	0
T18	771	0	0	0
T19	1290	0	0	0
T20	2780	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	106612844	161	0	0
CgEnOn_A	106612844	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106612844	161	0	0
T1	45110	0	0	0
T2	30597	0	0	0
T4	11154	0	0	0
T5	19337	0	0	0
T6	370	7	0	0
T7	515	0	0	0
T10	0	1	0	0
T17	408	3	0	0
T18	386	0	0	0
T19	645	0	0	0
T20	1390	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106612844	161	0	0
T1	45110	0	0	0
T2	30597	0	0	0
T4	11154	0	0	0
T5	19337	0	0	0
T6	370	7	0	0
T7	515	0	0	0
T10	0	1	0	0
T17	408	3	0	0
T18	386	0	0	0
T19	645	0	0	0
T20	1390	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	106612844	161	0	0
CgEnOn_A	106612844	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106612844	161	0	0
T1	45110	0	0	0
T2	30597	0	0	0
T4	11154	0	0	0
T5	19337	0	0	0
T6	370	7	0	0
T7	515	0	0	0
T10	0	1	0	0
T17	408	3	0	0
T18	386	0	0	0
T19	645	0	0	0
T20	1390	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106612844	161	0	0
T1	45110	0	0	0
T2	30597	0	0	0
T4	11154	0	0	0
T5	19337	0	0	0
T6	370	7	0	0
T7	515	0	0	0
T10	0	1	0	0
T17	408	3	0	0
T18	386	0	0	0
T19	645	0	0	0
T20	1390	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	106612844	161	0	0
CgEnOn_A	106612844	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106612844	161	0	0
T1	45110	0	0	0
T2	30597	0	0	0
T4	11154	0	0	0
T5	19337	0	0	0
T6	370	7	0	0
T7	515	0	0	0
T10	0	1	0	0
T17	408	3	0	0
T18	386	0	0	0
T19	645	0	0	0
T20	1390	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106612844	161	0	0
T1	45110	0	0	0
T2	30597	0	0	0
T4	11154	0	0	0
T5	19337	0	0	0
T6	370	7	0	0
T7	515	0	0	0
T10	0	1	0	0
T17	408	3	0	0
T18	386	0	0	0
T19	645	0	0	0
T20	1390	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	427507042	161	0	0
CgEnOn_A	427507042	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507042	161	0	0
T1	180519	0	0	0
T2	122452	0	0	0
T4	70610	0	0	0
T5	117709	0	0	0
T6	1614	7	0	0
T7	2124	0	0	0
T10	0	1	0	0
T17	1754	3	0	0
T18	1581	0	0	0
T19	2632	0	0	0
T20	5626	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507042	159	0	0
T1	180519	0	0	0
T2	122452	0	0	0
T4	70610	0	0	0
T5	117709	0	0	0
T6	1614	7	0	0
T7	2124	0	0	0
T10	0	1	0	0
T17	1754	3	0	0
T18	1581	0	0	0
T19	2632	0	0	0
T20	5626	0	0	0
T36	0	2	0	0
T44	0	2	0	0
T89	0	3	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	455832013	147	0	0
CgEnOn_A	455832013	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	147	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T16	0	1	0	0
T17	1839	5	0	0
T18	1647	0	0	0
T19	2742	0	0	0
T20	5860	0	0	0
T36	0	1	0	0
T44	0	3	0	0
T89	0	1	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	4	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	144	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T17	1839	5	0	0
T18	1647	0	0	0
T19	2742	0	0	0
T20	5860	0	0	0
T36	0	1	0	0
T44	0	3	0	0
T89	0	1	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	455832013	147	0	0
CgEnOn_A	455832013	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	147	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T16	0	1	0	0
T17	1839	5	0	0
T18	1647	0	0	0
T19	2742	0	0	0
T20	5860	0	0	0
T36	0	1	0	0
T44	0	3	0	0
T89	0	1	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	4	0	0
T151	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	144	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T17	1839	5	0	0
T18	1647	0	0	0
T19	2742	0	0	0
T20	5860	0	0	0
T36	0	1	0	0
T44	0	3	0	0
T89	0	1	0	0
T91	0	2	0	0
T93	0	3	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218609628	167	0	0
CgEnOn_A	218609628	165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218609628	167	0	0
T1	90264	0	0	0
T2	61229	0	0	0
T4	35306	0	0	0
T5	58857	0	0	0
T6	725	4	0	0
T7	1062	0	0	0
T17	880	5	0	0
T18	790	0	0	0
T19	1316	0	0	0
T20	2813	0	0	0
T36	0	2	0	0
T44	0	1	0	0
T89	0	2	0	0
T91	0	3	0	0
T93	0	6	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218609628	165	0	0
T1	90264	0	0	0
T2	61229	0	0	0
T4	35306	0	0	0
T5	58857	0	0	0
T6	725	4	0	0
T7	1062	0	0	0
T17	880	5	0	0
T18	790	0	0	0
T19	1316	0	0	0
T20	2813	0	0	0
T36	0	2	0	0
T44	0	1	0	0
T89	0	2	0	0
T91	0	3	0	0
T93	0	6	0	0
T150	0	4	0	0
T151	0	1	0	0
T152	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T36
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	106612844	7706	0	0
CgEnOn_A	106612844	5312	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106612844	7706	0	0
T1	45110	1	0	0
T2	30597	1	0	0
T4	11154	13	0	0
T5	19337	14	0	0
T6	370	8	0	0
T7	515	1	0	0
T17	408	4	0	0
T18	386	1	0	0
T19	645	1	0	0
T20	1390	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106612844	5312	0	0
T1	45110	0	0	0
T2	30597	0	0	0
T3	0	36	0	0
T4	11154	0	0	0
T5	19337	0	0	0
T6	370	7	0	0
T7	515	0	0	0
T10	0	99	0	0
T12	0	77	0	0
T17	408	3	0	0
T18	386	0	0	0
T19	645	0	0	0
T20	1390	0	0	0
T36	0	2	0	0
T65	0	9	0	0
T70	0	4	0	0
T72	0	7	0	0
T150	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T36
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	213227110	7735	0	0
CgEnOn_A	213227110	5341	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227110	7735	0	0
T1	90220	1	0	0
T2	61193	1	0	0
T4	22309	13	0	0
T5	38671	14	0	0
T6	740	8	0	0
T7	1030	1	0	0
T17	817	4	0	0
T18	771	1	0	0
T19	1290	1	0	0
T20	2780	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213227110	5341	0	0
T1	90220	0	0	0
T2	61193	0	0	0
T3	0	36	0	0
T4	22309	0	0	0
T5	38671	0	0	0
T6	740	7	0	0
T7	1030	0	0	0
T10	0	99	0	0
T12	0	73	0	0
T17	817	3	0	0
T18	771	0	0	0
T19	1290	0	0	0
T20	2780	0	0	0
T36	0	2	0	0
T65	0	9	0	0
T70	0	4	0	0
T72	0	6	0	0
T150	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T36
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	427507042	7755	0	0
CgEnOn_A	427507042	5359	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507042	7755	0	0
T1	180519	1	0	0
T2	122452	1	0	0
T4	70610	13	0	0
T5	117709	14	0	0
T6	1614	8	0	0
T7	2124	1	0	0
T17	1754	4	0	0
T18	1581	1	0	0
T19	2632	1	0	0
T20	5626	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427507042	5359	0	0
T1	180519	0	0	0
T2	122452	0	0	0
T3	0	34	0	0
T4	70610	0	0	0
T5	117709	0	0	0
T6	1614	7	0	0
T7	2124	0	0	0
T10	0	106	0	0
T12	0	78	0	0
T17	1754	3	0	0
T18	1581	0	0	0
T19	2632	0	0	0
T20	5626	0	0	0
T36	0	2	0	0
T65	0	11	0	0
T70	0	4	0	0
T72	0	6	0	0
T150	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T36
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218609628	7782	0	0
CgEnOn_A	218609628	5383	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218609628	7782	0	0
T1	90264	1	0	0
T2	61229	1	0	0
T4	35306	13	0	0
T5	58857	14	0	0
T6	725	5	0	0
T7	1062	1	0	0
T17	880	6	0	0
T18	790	1	0	0
T19	1316	1	0	0
T20	2813	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218609628	5383	0	0
T1	90264	0	0	0
T2	61229	0	0	0
T3	0	39	0	0
T4	35306	0	0	0
T5	58857	0	0	0
T6	725	4	0	0
T7	1062	0	0	0
T10	0	98	0	0
T12	0	81	0	0
T17	880	5	0	0
T18	790	0	0	0
T19	1316	0	0	0
T20	2813	0	0	0
T36	0	2	0	0
T65	0	9	0	0
T70	0	3	0	0
T72	0	7	0	0
T150	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Covered	T18,T20,T21
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	455832013	3870	0	0
CgEnOn_A	455832013	3867	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	3870	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T3	0	16	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T10	0	41	0	0
T17	1839	5	0	0
T18	1647	1	0	0
T19	2742	0	0	0
T20	5860	4	0	0
T21	0	10	0	0
T35	0	4	0	0
T36	0	1	0	0
T116	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	3867	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T3	0	16	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T10	0	41	0	0
T17	1839	5	0	0
T18	1647	1	0	0
T19	2742	0	0	0
T20	5860	4	0	0
T21	0	10	0	0
T35	0	4	0	0
T36	0	1	0	0
T116	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Covered	T20,T21,T35
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	455832013	3912	0	0
CgEnOn_A	455832013	3909	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	3912	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T3	0	20	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T10	0	51	0	0
T17	1839	5	0	0
T18	1647	0	0	0
T19	2742	0	0	0
T20	5860	4	0	0
T21	0	10	0	0
T35	0	6	0	0
T36	0	1	0	0
T73	0	1	0	0
T116	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	3909	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T3	0	20	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T10	0	51	0	0
T17	1839	5	0	0
T18	1647	0	0	0
T19	2742	0	0	0
T20	5860	4	0	0
T21	0	10	0	0
T35	0	6	0	0
T36	0	1	0	0
T73	0	1	0	0
T116	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Covered	T20,T21,T35
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	455832013	3892	0	0
CgEnOn_A	455832013	3889	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	3892	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T3	0	20	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T10	0	43	0	0
T17	1839	5	0	0
T18	1647	0	0	0
T19	2742	0	0	0
T20	5860	3	0	0
T21	0	9	0	0
T35	0	1	0	0
T36	0	1	0	0
T73	0	1	0	0
T116	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	3889	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T3	0	20	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T10	0	43	0	0
T17	1839	5	0	0
T18	1647	0	0	0
T19	2742	0	0	0
T20	5860	3	0	0
T21	0	9	0	0
T35	0	1	0	0
T36	0	1	0	0
T73	0	1	0	0
T116	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T5
1	0	Covered	T18,T21,T35
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	455832013	3907	0	0
CgEnOn_A	455832013	3904	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	3907	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T3	0	15	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T10	0	50	0	0
T17	1839	5	0	0
T18	1647	1	0	0
T19	2742	0	0	0
T20	5860	0	0	0
T21	0	13	0	0
T35	0	4	0	0
T36	0	1	0	0
T73	0	1	0	0
T116	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455832013	3904	0	0
T1	188046	0	0	0
T2	127558	0	0	0
T3	0	15	0	0
T4	73554	0	0	0
T5	122618	0	0	0
T6	1647	4	0	0
T7	2213	0	0	0
T10	0	50	0	0
T17	1839	5	0	0
T18	1647	1	0	0
T19	2742	0	0	0
T20	5860	0	0	0
T21	0	13	0	0
T35	0	4	0	0
T36	0	1	0	0
T73	0	1	0	0
T116	0	8	0	0