Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 93.75 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

16 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack 0.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 6 0 0.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_status.ack
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 6 0 0.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.extclk_ctrl.sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.jitter_enable.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_all_clk_byp_ack_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_div_step_down_req_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_0_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_1_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_2_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_idle_3_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_io_clk_byp_ack_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 6 0 0.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
false 0 1 1
true 0 1 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 159 1 T9 1 T22 1 T82 2
others[1] 190 1 T7 1 T9 1 T20 1
others[2] 3911 1 T7 13 T9 7 T20 20
others[3] 327 1 T20 4 T22 1 T109 1
false 839 1 T7 3 T9 1 T20 7
true 2579 1 T7 9 T9 4 T20 6


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 109 1 T7 1 T9 1 T82 1
others[1] 137 1 T109 1 T100 1 T29 1
others[2] 3815 1 T7 14 T9 7 T20 19
others[3] 162 1 T7 1 T109 1 T82 2
false 460 1 T20 1 T4 10 T109 1
true 3322 1 T7 10 T9 6 T20 18


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 532 1 T1 4 T6 1 T4 2
others[1] 525 1 T1 2 T4 1 T24 2
others[2] 528 1 T1 2 T24 1 T5 1
others[3] 924 1 T1 8 T6 1 T4 3
false 3651 1 T1 17 T6 4 T4 10
true 872 1 T1 1 T6 2 T4 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 538 1 T1 5 T4 1 T24 3
others[1] 532 1 T1 1 T6 1 T4 1
others[2] 582 1 T1 4 T6 1 T4 2
others[3] 863 1 T1 5 T6 2 T4 4
false 3646 1 T1 17 T6 4 T4 11
true 871 1 T1 2 T4 1 T24 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 543 1 T4 1 T24 5 T5 1
others[1] 566 1 T1 4 T4 1 T24 2
others[2] 555 1 T1 6 T5 2 T2 2
others[3] 831 1 T1 2 T6 3 T4 2
false 3661 1 T1 17 T6 4 T4 12
true 876 1 T1 5 T6 1 T4 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2185 1 T2 19 T14 19 T113 19
others[1] 345 1 T2 3 T14 3 T113 3
others[2] 345 1 T2 3 T14 3 T113 3
others[3] 575 1 T2 5 T14 5 T113 5
false 115 1 T2 1 T14 1 T113 1
true 115 1 T2 1 T14 1 T113 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 523 1 T1 2 T24 3 T5 2
others[1] 540 1 T1 4 T4 1 T24 1
others[2] 553 1 T1 3 T6 1 T4 1
others[3] 869 1 T1 3 T6 1 T4 1
false 3677 1 T1 17 T6 4 T4 14
true 870 1 T1 5 T6 2 T4 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 550 1 T1 1 T6 2 T4 1
others[1] 515 1 T1 4 T4 2 T24 2
others[2] 568 1 T1 1 T4 1 T24 1
others[3] 843 1 T1 5 T6 2 T4 1
false 3649 1 T1 17 T6 4 T4 12
true 907 1 T1 6 T4 3 T24 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 1563 1 T9 3 T20 2 T109 2
others[1] 1468 1 T7 1 T9 3 T20 4
others[2] 1437 1 T9 2 T20 5 T109 1
others[3] 2423 1 T7 2 T9 3 T20 8
false 5351 1 T7 4 T8 1 T9 3
true 3964 1 T7 4 T9 3 T20 13


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 1981 1 T9 1 T20 3 T109 1
others[1] 1996 1 T7 2 T20 4 T22 5
others[2] 1961 1 T7 2 T9 1 T20 2
others[3] 3284 1 T7 2 T9 4 T20 7
false 5983 1 T7 3 T8 1 T9 6
true 6604 1 T7 4 T9 5 T20 13


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 713 1 T25 1 T37 6 T2 1
others[1] 106 1 T25 2 T37 1 T78 4
others[2] 107 1 T25 5 T37 4 T78 4
others[3] 177 1 T25 4 T37 3 T78 6
false 10451 1 T7 3 T8 1 T9 2
true 11739 1 T7 4 T8 1 T9 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 707 1 T25 3 T37 3 T2 1
others[1] 106 1 T25 1 T37 4 T78 4
others[2] 103 1 T25 2 T37 3 T80 1
others[3] 188 1 T25 6 T37 4 T78 6
false 10335 1 T7 3 T9 2 T1 8
true 11635 1 T7 3 T8 1 T9 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 684 1 T25 2 T37 3 T2 1
others[1] 114 1 T25 3 T37 1 T78 5
others[2] 112 1 T25 2 T37 3 T78 3
others[3] 194 1 T25 5 T37 7 T78 7
false 10358 1 T7 4 T9 3 T1 5
true 11665 1 T7 5 T8 1 T9 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 708 1 T25 1 T37 1 T2 1
others[1] 99 1 T25 2 T37 4 T78 2
others[2] 99 1 T25 2 T37 1 T78 5
others[3] 198 1 T25 7 T37 8 T78 6
false 10456 1 T7 3 T8 1 T9 2
true 11721 1 T7 4 T8 1 T9 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 930 1 T7 1 T9 4 T20 3
others[1] 957 1 T20 4 T22 2 T109 1
others[2] 954 1 T20 2 T109 3 T100 2
others[3] 1591 1 T9 3 T20 6 T22 1
false 4871 1 T7 1 T8 1 T9 5
true 5191 1 T7 1 T9 4 T20 10

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