Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	576606	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3275417

1

T7

14

T8

1

T9

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	951068	1			T7	13		T9	12		T1	41
values[0x0]	1333607	1			T7	9		T8	1		T9	5
values[0x1]	1567348	1			T7	18		T8	2		T9	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	320616	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3531407

1

T7

18

T8

1

T9

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13975	1			T24	1		T5	3		T82	5
valid_sources[0x01]	14004	1			T5	3		T2	1		T110	2
valid_sources[0x02]	13402	1			T24	1		T5	1		T2	8
valid_sources[0x03]	13918	1			T1	3		T24	2		T5	2
valid_sources[0x04]	15781	1			T6	2		T109	1		T3	490
valid_sources[0x05]	14173	1			T24	2		T37	1		T2	4
valid_sources[0x06]	14979	1			T6	1		T5	4		T3	613
valid_sources[0x07]	18081	1			T5	1		T37	1		T109	2
valid_sources[0x08]	17655	1			T24	1		T5	4		T37	1
valid_sources[0x09]	14757	1			T24	1		T5	2		T2	4
valid_sources[0x0a]	15452	1			T24	1		T5	2		T3	446
valid_sources[0x0b]	15953	1			T5	3		T2	2		T3	539
valid_sources[0x0c]	15164	1			T6	2		T5	5		T37	1
valid_sources[0x0d]	14812	1			T7	40		T24	2		T5	5
valid_sources[0x0e]	15580	1			T2	2		T3	444		T78	2
valid_sources[0x0f]	15698	1			T24	2		T5	4		T2	6
valid_sources[0x10]	14868	1			T24	2		T5	2		T37	1
valid_sources[0x11]	14736	1			T24	1		T5	3		T37	1
valid_sources[0x12]	14386	1			T5	2		T2	3		T3	446
valid_sources[0x13]	15690	1			T4	470		T24	1		T5	3
valid_sources[0x14]	13862	1			T1	7		T24	4		T5	2
valid_sources[0x15]	14923	1			T1	16		T5	4		T37	2
valid_sources[0x16]	15083	1			T5	3		T37	1		T3	473
valid_sources[0x17]	15190	1			T24	1		T5	1		T2	4
valid_sources[0x18]	14895	1			T6	1		T24	2		T5	1
valid_sources[0x19]	15274	1			T5	4		T2	2		T3	506
valid_sources[0x1a]	13583	1			T5	5		T2	5		T3	486
valid_sources[0x1b]	15205	1			T24	7		T5	11		T3	561
valid_sources[0x1c]	13770	1			T6	1		T24	1		T5	4
valid_sources[0x1d]	15590	1			T1	4		T5	1		T2	1
valid_sources[0x1e]	14889	1			T6	1		T5	1		T3	496
valid_sources[0x1f]	14410	1			T1	1		T24	1		T5	2
valid_sources[0x20]	14627	1			T6	1		T5	4		T2	1
valid_sources[0x21]	15791	1			T5	2		T2	3		T3	494
valid_sources[0x22]	15249	1			T1	3		T6	2		T24	1
valid_sources[0x23]	15612	1			T24	1		T2	1		T3	492
valid_sources[0x24]	16064	1			T1	3		T6	2		T5	1
valid_sources[0x25]	14575	1			T1	1		T5	2		T3	405
valid_sources[0x26]	14621	1			T6	2		T5	2		T37	1
valid_sources[0x27]	14563	1			T1	5		T2	7		T82	3
valid_sources[0x28]	14256	1			T1	1		T6	1		T24	1
valid_sources[0x29]	17235	1			T24	1		T2	1		T3	435
valid_sources[0x2a]	15469	1			T1	4		T6	1		T5	1
valid_sources[0x2b]	15596	1			T1	5		T5	2		T37	2
valid_sources[0x2c]	15555	1			T20	6		T5	1		T3	538
valid_sources[0x2d]	14519	1			T5	9		T3	498		T29	3
valid_sources[0x2e]	15140	1			T5	2		T109	1		T2	2
valid_sources[0x2f]	15011	1			T5	2		T3	470		T75	2
valid_sources[0x30]	16069	1			T6	1		T24	4		T2	3
valid_sources[0x31]	14980	1			T1	2		T2	1		T3	514
valid_sources[0x32]	15707	1			T1	7		T5	2		T37	1
valid_sources[0x33]	15373	1			T1	1		T24	2		T5	2
valid_sources[0x34]	15215	1			T1	4		T5	7		T100	4
valid_sources[0x35]	17503	1			T6	6		T21	70		T24	2
valid_sources[0x36]	15509	1			T8	1		T1	10		T5	5
valid_sources[0x37]	15565	1			T24	2		T5	5		T37	1
valid_sources[0x38]	16153	1			T5	3		T2	10		T3	470
valid_sources[0x39]	16928	1			T5	3		T2	4		T82	1
valid_sources[0x3a]	14674	1			T22	2		T24	1		T5	1
valid_sources[0x3b]	14131	1			T8	1		T6	1		T24	2
valid_sources[0x3c]	14827	1			T5	2		T2	7		T3	501
valid_sources[0x3d]	15647	1			T1	7		T5	2		T2	2
valid_sources[0x3e]	14569	1			T1	3		T20	6		T24	1
valid_sources[0x3f]	14482	1			T24	1		T5	1		T3	518
valid_sources[0x40]	13569	1			T6	2		T5	3		T3	512
valid_sources[0x41]	13946	1			T24	1		T5	4		T3	490
valid_sources[0x42]	15342	1			T1	4		T24	2		T5	4
valid_sources[0x43]	15509	1			T22	1		T5	2		T100	4
valid_sources[0x44]	15946	1			T6	2		T24	4		T109	1
valid_sources[0x45]	15306	1			T5	3		T109	1		T3	516
valid_sources[0x46]	14796	1			T6	3		T5	3		T109	1
valid_sources[0x47]	14708	1			T1	11		T22	2		T5	5
valid_sources[0x48]	14842	1			T24	1		T5	1		T37	2
valid_sources[0x49]	15948	1			T5	2		T37	1		T3	414
valid_sources[0x4a]	14608	1			T24	1		T5	3		T37	1
valid_sources[0x4b]	13763	1			T24	1		T5	4		T2	4
valid_sources[0x4c]	13038	1			T24	2		T2	2		T3	455
valid_sources[0x4d]	15299	1			T24	2		T5	2		T109	1
valid_sources[0x4e]	15446	1			T22	1		T24	2		T5	2
valid_sources[0x4f]	14706	1			T1	2		T24	2		T5	2
valid_sources[0x50]	15092	1			T20	5		T24	1		T5	2
valid_sources[0x51]	14167	1			T1	7		T5	3		T37	1
valid_sources[0x52]	13642	1			T1	2		T5	5		T2	3
valid_sources[0x53]	14810	1			T1	2		T24	1		T5	4
valid_sources[0x54]	15722	1			T24	5		T5	2		T3	442
valid_sources[0x55]	13685	1			T24	5		T5	8		T37	2
valid_sources[0x56]	15030	1			T5	6		T37	1		T109	2
valid_sources[0x57]	14473	1			T24	1		T5	3		T2	1
valid_sources[0x58]	15640	1			T20	1		T6	1		T24	2
valid_sources[0x59]	14546	1			T110	2		T3	512		T78	1
valid_sources[0x5a]	13798	1			T1	3		T6	2		T24	4
valid_sources[0x5b]	16050	1			T5	2		T2	4		T3	536
valid_sources[0x5c]	15937	1			T1	2		T24	2		T5	3
valid_sources[0x5d]	15548	1			T1	12		T6	2		T24	2
valid_sources[0x5e]	14542	1			T1	5		T24	2		T5	9
valid_sources[0x5f]	16616	1			T1	1		T5	1		T3	432
valid_sources[0x60]	12470	1			T6	2		T5	1		T110	1
valid_sources[0x61]	14624	1			T24	2		T5	3		T110	1
valid_sources[0x62]	15607	1			T24	2		T5	2		T2	3
valid_sources[0x63]	15130	1			T24	1		T5	1		T3	578
valid_sources[0x64]	14353	1			T9	1		T1	9		T24	1
valid_sources[0x65]	14679	1			T6	1		T24	4		T5	5
valid_sources[0x66]	13186	1			T1	22		T5	4		T3	421
valid_sources[0x67]	14288	1			T9	1		T1	2		T5	5
valid_sources[0x68]	14284	1			T6	2		T24	3		T5	3
valid_sources[0x69]	14748	1			T1	3		T24	2		T5	3
valid_sources[0x6a]	13666	1			T1	7		T5	2		T2	4
valid_sources[0x6b]	16052	1			T6	3		T24	7		T5	4
valid_sources[0x6c]	12801	1			T1	2		T24	2		T5	1
valid_sources[0x6d]	14378	1			T5	1		T37	1		T3	477
valid_sources[0x6e]	14604	1			T1	5		T6	1		T24	1
valid_sources[0x6f]	13647	1			T1	4		T6	1		T5	1
valid_sources[0x70]	14215	1			T1	11		T6	3		T5	3
valid_sources[0x71]	17514	1			T1	11		T24	4		T37	1
valid_sources[0x72]	14736	1			T24	1		T5	2		T37	2
valid_sources[0x73]	16344	1			T2	3		T3	546		T29	5
valid_sources[0x74]	13780	1			T1	6		T20	1		T24	2
valid_sources[0x75]	15304	1			T1	5		T6	4		T24	4
valid_sources[0x76]	16209	1			T5	2		T2	4		T3	435
valid_sources[0x77]	13971	1			T1	8		T6	2		T37	1
valid_sources[0x78]	15706	1			T1	7		T24	1		T5	6
valid_sources[0x79]	15688	1			T9	14		T5	1		T37	1
valid_sources[0x7a]	15309	1			T5	2		T37	1		T2	5
valid_sources[0x7b]	17692	1			T1	5		T24	2		T5	5
valid_sources[0x7c]	17087	1			T1	2		T24	2		T5	2
valid_sources[0x7d]	14243	1			T1	4		T6	1		T24	1
valid_sources[0x7e]	15434	1			T24	6		T5	3		T100	5
valid_sources[0x7f]	13881	1			T24	1		T5	2		T37	1
valid_sources[0x80]	16726	1			T24	2		T5	1		T2	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

828734

1

T7

8

T9

5

T1

24

values[0x0]

all_enables

biggest_size

1244895

1

T7

3

T1

96

T20

6

values[0x1]

all_enables

biggest_size

1201788

1

T7

3

T8

1

T9

3