Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
312954 |
1 |
|
|
T7 |
2 |
|
T8 |
9 |
|
T9 |
2 |
auto[1] |
181153999 |
1 |
|
|
T7 |
781 |
|
T8 |
638 |
|
T9 |
11129 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8572 |
1 |
|
|
T7 |
2 |
|
T8 |
2 |
|
T9 |
2 |
auto[1] |
181458381 |
1 |
|
|
T7 |
781 |
|
T8 |
645 |
|
T9 |
11129 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
112931078 |
1 |
|
|
T7 |
207 |
|
T8 |
10 |
|
T9 |
10347 |
auto[1] |
68535875 |
1 |
|
|
T7 |
576 |
|
T8 |
637 |
|
T9 |
784 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5204 |
1 |
|
|
T8 |
2 |
|
T9 |
2 |
|
T20 |
2 |
auto[0] |
auto[0] |
auto[1] |
1502 |
1 |
|
|
T7 |
2 |
|
T1 |
2 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[0] |
246410 |
1 |
|
|
T1 |
115 |
|
T2 |
190 |
|
T3 |
818 |
auto[0] |
auto[1] |
auto[1] |
59838 |
1 |
|
|
T8 |
7 |
|
T1 |
56 |
|
T2 |
116 |
auto[1] |
auto[1] |
auto[0] |
112677598 |
1 |
|
|
T7 |
207 |
|
T8 |
8 |
|
T9 |
10345 |
auto[1] |
auto[1] |
auto[1] |
68474535 |
1 |
|
|
T7 |
574 |
|
T8 |
630 |
|
T9 |
784 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168041 |
1 |
|
|
T7 |
2 |
|
T8 |
5 |
|
T9 |
2 |
auto[1] |
90563556 |
1 |
|
|
T7 |
390 |
|
T8 |
319 |
|
T9 |
5562 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7649 |
1 |
|
|
T7 |
2 |
|
T8 |
2 |
|
T9 |
2 |
auto[1] |
90723948 |
1 |
|
|
T7 |
390 |
|
T8 |
322 |
|
T9 |
5562 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56463648 |
1 |
|
|
T7 |
103 |
|
T8 |
6 |
|
T9 |
5172 |
auto[1] |
34267949 |
1 |
|
|
T7 |
289 |
|
T8 |
318 |
|
T9 |
392 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5204 |
1 |
|
|
T8 |
2 |
|
T9 |
2 |
|
T20 |
2 |
auto[0] |
auto[0] |
auto[1] |
1502 |
1 |
|
|
T7 |
2 |
|
T1 |
2 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[0] |
130780 |
1 |
|
|
T1 |
60 |
|
T2 |
90 |
|
T3 |
413 |
auto[0] |
auto[1] |
auto[1] |
30555 |
1 |
|
|
T8 |
3 |
|
T1 |
24 |
|
T2 |
63 |
auto[1] |
auto[1] |
auto[0] |
56326721 |
1 |
|
|
T7 |
103 |
|
T8 |
4 |
|
T9 |
5170 |
auto[1] |
auto[1] |
auto[1] |
34235892 |
1 |
|
|
T7 |
287 |
|
T8 |
315 |
|
T9 |
392 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
665913 |
1 |
|
|
T7 |
2 |
|
T8 |
16 |
|
T9 |
2 |
auto[1] |
361748405 |
1 |
|
|
T7 |
1512 |
|
T8 |
1279 |
|
T9 |
18728 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10448 |
1 |
|
|
T7 |
2 |
|
T8 |
2 |
|
T9 |
2 |
auto[1] |
362403870 |
1 |
|
|
T7 |
1512 |
|
T8 |
1293 |
|
T9 |
18728 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
225342642 |
1 |
|
|
T7 |
362 |
|
T8 |
21 |
|
T9 |
17162 |
auto[1] |
137071676 |
1 |
|
|
T7 |
1152 |
|
T8 |
1274 |
|
T9 |
1568 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5204 |
1 |
|
|
T8 |
2 |
|
T9 |
2 |
|
T20 |
2 |
auto[0] |
auto[0] |
auto[1] |
1502 |
1 |
|
|
T7 |
2 |
|
T1 |
2 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[0] |
532761 |
1 |
|
|
T1 |
207 |
|
T2 |
360 |
|
T3 |
1367 |
auto[0] |
auto[1] |
auto[1] |
126446 |
1 |
|
|
T8 |
14 |
|
T1 |
113 |
|
T2 |
252 |
auto[1] |
auto[1] |
auto[0] |
224800935 |
1 |
|
|
T7 |
362 |
|
T8 |
19 |
|
T9 |
17160 |
auto[1] |
auto[1] |
auto[1] |
136943728 |
1 |
|
|
T7 |
1150 |
|
T8 |
1260 |
|
T9 |
1568 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
297218 |
1 |
|
|
T7 |
2 |
|
T8 |
9 |
|
T9 |
2 |
auto[1] |
185360652 |
1 |
|
|
T7 |
755 |
|
T8 |
638 |
|
T9 |
9363 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8224 |
1 |
|
|
T7 |
2 |
|
T8 |
2 |
|
T9 |
2 |
auto[1] |
185649646 |
1 |
|
|
T7 |
755 |
|
T8 |
645 |
|
T9 |
9363 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
115064041 |
1 |
|
|
T7 |
182 |
|
T8 |
10 |
|
T9 |
8581 |
auto[1] |
70593829 |
1 |
|
|
T7 |
575 |
|
T8 |
637 |
|
T9 |
784 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5192 |
1 |
|
|
T8 |
2 |
|
T9 |
2 |
|
T20 |
2 |
auto[0] |
auto[0] |
auto[1] |
1514 |
1 |
|
|
T7 |
2 |
|
T1 |
2 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[0] |
230517 |
1 |
|
|
T1 |
111 |
|
T2 |
190 |
|
T3 |
740 |
auto[0] |
auto[1] |
auto[1] |
59995 |
1 |
|
|
T8 |
7 |
|
T1 |
57 |
|
T2 |
116 |
auto[1] |
auto[1] |
auto[0] |
114826814 |
1 |
|
|
T7 |
182 |
|
T8 |
8 |
|
T9 |
8579 |
auto[1] |
auto[1] |
auto[1] |
70532320 |
1 |
|
|
T7 |
573 |
|
T8 |
630 |
|
T9 |
784 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |