Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T4
0	1	Covered	T8,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T4
1	0	Covered	T23,T38,T39
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	823134460	13750	0	0
GateOpen_A	823134460	20328	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823134460	13750	0	0
T1	436843	56	0	0
T2	0	40	0	0
T3	0	336	0	0
T4	124682	0	0	0
T5	206552	0	0	0
T6	120812	0	0	0
T14	0	153	0	0
T20	5425	0	0	0
T21	14538	0	0	0
T22	9966	0	0	0
T23	3058	11	0	0
T24	228757	0	0	0
T25	7950	0	0	0
T29	0	124	0	0
T75	0	31	0	0
T76	0	9	0	0
T113	0	4	0	0
T165	0	22	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823134460	20328	0	0
T1	436843	56	0	0
T4	124682	40	0	0
T5	0	68	0	0
T6	120812	0	0	0
T8	3149	4	0	0
T9	45242	4	0	0
T20	5425	4	0	0
T21	14538	0	0	0
T22	9966	4	0	0
T23	3058	15	0	0
T24	228757	0	0	0
T37	0	4	0	0
T109	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T4
0	1	Covered	T8,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T4
1	0	Covered	T23,T38,T39
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	90672879	3256	0	0
GateOpen_A	90672879	4898	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672879	3256	0	0
T1	48529	14	0	0
T2	0	11	0	0
T3	0	77	0	0
T4	8154	0	0	0
T5	15095	0	0	0
T6	13406	0	0	0
T14	0	38	0	0
T20	644	0	0	0
T21	1593	0	0	0
T22	1142	0	0	0
T23	335	3	0	0
T24	23482	0	0	0
T25	870	0	0	0
T29	0	29	0	0
T75	0	6	0	0
T76	0	2	0	0
T113	0	1	0	0
T165	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672879	4898	0	0
T1	48529	14	0	0
T4	8154	10	0	0
T5	0	17	0	0
T6	13406	0	0	0
T8	335	1	0	0
T9	5593	1	0	0
T20	644	1	0	0
T21	1593	0	0	0
T22	1142	1	0	0
T23	335	4	0	0
T24	23482	0	0	0
T37	0	1	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T4
0	1	Covered	T8,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T4
1	0	Covered	T23,T38,T39
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	181346572	3519	0	0
GateOpen_A	181346572	5161	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181346572	3519	0	0
T1	97058	13	0	0
T2	0	9	0	0
T3	0	84	0	0
T4	16310	0	0	0
T5	30188	0	0	0
T6	26811	0	0	0
T14	0	39	0	0
T20	1290	0	0	0
T21	3186	0	0	0
T22	2284	0	0	0
T23	669	3	0	0
T24	46963	0	0	0
T25	1740	0	0	0
T29	0	30	0	0
T75	0	8	0	0
T76	0	2	0	0
T113	0	1	0	0
T165	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181346572	5161	0	0
T1	97058	13	0	0
T4	16310	10	0	0
T5	0	17	0	0
T6	26811	0	0	0
T8	669	1	0	0
T9	11186	1	0	0
T20	1290	1	0	0
T21	3186	0	0	0
T22	2284	1	0	0
T23	669	4	0	0
T24	46963	0	0	0
T37	0	1	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T4
0	1	Covered	T8,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T4
1	0	Covered	T23,T38,T39
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	364425001	3497	0	0
GateOpen_A	364425001	5144	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364425001	3497	0	0
T1	194167	15	0	0
T2	0	9	0	0
T3	0	91	0	0
T4	66811	0	0	0
T5	107511	0	0	0
T6	53729	0	0	0
T14	0	38	0	0
T20	2327	0	0	0
T21	6506	0	0	0
T22	4360	0	0	0
T23	1362	3	0	0
T24	94020	0	0	0
T25	3560	0	0	0
T29	0	33	0	0
T75	0	9	0	0
T76	0	2	0	0
T113	0	1	0	0
T165	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364425001	5144	0	0
T1	194167	15	0	0
T4	66811	10	0	0
T5	0	17	0	0
T6	53729	0	0	0
T8	1430	1	0	0
T9	18975	1	0	0
T20	2327	1	0	0
T21	6506	0	0	0
T22	4360	1	0	0
T23	1362	4	0	0
T24	94020	0	0	0
T37	0	1	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T4
0	1	Covered	T8,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T4
1	0	Covered	T23,T38,T39
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	186690008	3478	0	0
GateOpen_A	186690008	5125	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186690008	3478	0	0
T1	97089	14	0	0
T2	0	11	0	0
T3	0	84	0	0
T4	33407	0	0	0
T5	53758	0	0	0
T6	26866	0	0	0
T14	0	38	0	0
T20	1164	0	0	0
T21	3253	0	0	0
T22	2180	0	0	0
T23	692	2	0	0
T24	64292	0	0	0
T25	1780	0	0	0
T29	0	32	0	0
T75	0	8	0	0
T76	0	3	0	0
T113	0	1	0	0
T165	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186690008	5125	0	0
T1	97089	14	0	0
T4	33407	10	0	0
T5	0	17	0	0
T6	26866	0	0	0
T8	715	1	0	0
T9	9488	1	0	0
T20	1164	1	0	0
T21	3253	0	0	0
T22	2180	1	0	0
T23	692	3	0	0
T24	64292	0	0	0
T37	0	1	0	0
T109	0	1	0	0