Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	756184175	77785	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756184175	77785	0	0
T1	970830	305	0	0
T2	0	72	0	0
T3	0	2013	0	0
T4	347980	0	0	0
T5	223985	0	0	0
T6	19590	0	0	0
T13	0	305	0	0
T14	0	1174	0	0
T15	0	83	0	0
T16	0	341	0	0
T17	0	3973	0	0
T18	0	418	0	0
T19	0	611	0	0
T20	11760	0	0	0
T21	15920	0	0	0
T22	5445	0	0	0
T23	6555	0	0	0
T24	722395	0	0	0
T25	9450	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151236835	11282	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	11282	0	0
T1	194166	45	0	0
T2	0	14	0	0
T3	0	298	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T6	3918	0	0	0
T13	0	40	0	0
T14	0	151	0	0
T15	0	13	0	0
T16	0	49	0	0
T17	0	526	0	0
T18	0	62	0	0
T19	0	98	0	0
T20	2352	0	0	0
T21	3184	0	0	0
T22	1089	0	0	0
T23	1311	0	0	0
T24	144479	0	0	0
T25	1890	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151236835	10924	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	10924	0	0
T1	194166	38	0	0
T2	0	14	0	0
T3	0	256	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T6	3918	0	0	0
T13	0	39	0	0
T14	0	168	0	0
T15	0	13	0	0
T16	0	47	0	0
T17	0	517	0	0
T18	0	52	0	0
T19	0	96	0	0
T20	2352	0	0	0
T21	3184	0	0	0
T22	1089	0	0	0
T23	1311	0	0	0
T24	144479	0	0	0
T25	1890	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151236835	15710	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	15710	0	0
T1	194166	59	0	0
T2	0	14	0	0
T3	0	396	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T6	3918	0	0	0
T13	0	63	0	0
T14	0	232	0	0
T15	0	17	0	0
T16	0	70	0	0
T17	0	802	0	0
T18	0	82	0	0
T19	0	124	0	0
T20	2352	0	0	0
T21	3184	0	0	0
T22	1089	0	0	0
T23	1311	0	0	0
T24	144479	0	0	0
T25	1890	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151236835	15638	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	15638	0	0
T1	194166	62	0	0
T2	0	14	0	0
T3	0	407	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T6	3918	0	0	0
T13	0	62	0	0
T14	0	235	0	0
T15	0	17	0	0
T16	0	68	0	0
T17	0	802	0	0
T18	0	86	0	0
T19	0	124	0	0
T20	2352	0	0	0
T21	3184	0	0	0
T22	1089	0	0	0
T23	1311	0	0	0
T24	144479	0	0	0
T25	1890	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151236835	24231	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	24231	0	0
T1	194166	101	0	0
T2	0	16	0	0
T3	0	656	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T6	3918	0	0	0
T13	0	101	0	0
T14	0	388	0	0
T15	0	23	0	0
T16	0	107	0	0
T17	0	1326	0	0
T18	0	136	0	0
T19	0	169	0	0
T20	2352	0	0	0
T21	3184	0	0	0
T22	1089	0	0	0
T23	1311	0	0	0
T24	144479	0	0	0
T25	1890	0	0	0