Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22512 |
22512 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T8 |
28 |
28 |
0 |
0 |
T9 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
T21 |
28 |
28 |
0 |
0 |
T22 |
28 |
28 |
0 |
0 |
T23 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5169706 |
5165139 |
0 |
0 |
T4 |
1792196 |
231538 |
0 |
0 |
T6 |
733110 |
731156 |
0 |
0 |
T7 |
43429 |
40814 |
0 |
0 |
T8 |
38822 |
35348 |
0 |
0 |
T9 |
258698 |
255861 |
0 |
0 |
T20 |
62494 |
56775 |
0 |
0 |
T21 |
126610 |
123423 |
0 |
0 |
T22 |
70436 |
66597 |
0 |
0 |
T23 |
35904 |
33796 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
907421010 |
889425078 |
0 |
14472 |
T1 |
1164996 |
1163838 |
0 |
18 |
T4 |
417576 |
32196 |
0 |
18 |
T6 |
23508 |
23418 |
0 |
18 |
T7 |
9834 |
9168 |
0 |
18 |
T8 |
8934 |
8070 |
0 |
18 |
T9 |
7110 |
7002 |
0 |
18 |
T20 |
14112 |
12696 |
0 |
18 |
T21 |
19104 |
18570 |
0 |
18 |
T22 |
6534 |
6108 |
0 |
18 |
T23 |
7866 |
7344 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16884 |
T1 |
1391554 |
1390171 |
0 |
21 |
T4 |
484386 |
37345 |
0 |
21 |
T6 |
285440 |
284557 |
0 |
21 |
T7 |
11656 |
10863 |
0 |
21 |
T8 |
10363 |
9362 |
0 |
21 |
T9 |
100409 |
99093 |
0 |
21 |
T20 |
16727 |
15050 |
0 |
21 |
T21 |
39981 |
38880 |
0 |
21 |
T22 |
24701 |
23136 |
0 |
21 |
T23 |
9820 |
9150 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
193726 |
0 |
0 |
T1 |
1391554 |
92 |
0 |
0 |
T3 |
0 |
861 |
0 |
0 |
T4 |
484386 |
44 |
0 |
0 |
T6 |
285440 |
4 |
0 |
0 |
T7 |
11656 |
88 |
0 |
0 |
T8 |
10363 |
6 |
0 |
0 |
T9 |
100409 |
111 |
0 |
0 |
T20 |
16727 |
234 |
0 |
0 |
T21 |
39981 |
82 |
0 |
0 |
T22 |
24701 |
58 |
0 |
0 |
T23 |
9820 |
50 |
0 |
0 |
T77 |
0 |
44 |
0 |
0 |
T82 |
0 |
125 |
0 |
0 |
T100 |
0 |
124 |
0 |
0 |
T109 |
0 |
85 |
0 |
0 |
T110 |
0 |
129 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2613156 |
2611091 |
0 |
0 |
T4 |
890234 |
161448 |
0 |
0 |
T6 |
424162 |
423142 |
0 |
0 |
T7 |
21939 |
20744 |
0 |
0 |
T8 |
19525 |
17877 |
0 |
0 |
T9 |
151179 |
149727 |
0 |
0 |
T20 |
31655 |
28990 |
0 |
0 |
T21 |
67525 |
65934 |
0 |
0 |
T22 |
39201 |
37314 |
0 |
0 |
T23 |
18218 |
17263 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
364424552 |
359972062 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
66810 |
5182 |
0 |
0 |
T6 |
53728 |
53566 |
0 |
0 |
T7 |
1622 |
1514 |
0 |
0 |
T8 |
1429 |
1295 |
0 |
0 |
T9 |
18975 |
18730 |
0 |
0 |
T20 |
2327 |
2097 |
0 |
0 |
T21 |
6505 |
6329 |
0 |
0 |
T22 |
4359 |
4087 |
0 |
0 |
T23 |
1362 |
1269 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
364424552 |
359965236 |
0 |
2412 |
T1 |
194166 |
193973 |
0 |
3 |
T4 |
66810 |
5149 |
0 |
3 |
T6 |
53728 |
53563 |
0 |
3 |
T7 |
1622 |
1511 |
0 |
3 |
T8 |
1429 |
1292 |
0 |
3 |
T9 |
18975 |
18727 |
0 |
3 |
T20 |
2327 |
2094 |
0 |
3 |
T21 |
6505 |
6326 |
0 |
3 |
T22 |
4359 |
4084 |
0 |
3 |
T23 |
1362 |
1266 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
364424552 |
27670 |
0 |
0 |
T1 |
194166 |
0 |
0 |
0 |
T3 |
0 |
347 |
0 |
0 |
T4 |
66810 |
0 |
0 |
0 |
T6 |
53728 |
0 |
0 |
0 |
T7 |
1622 |
18 |
0 |
0 |
T8 |
1429 |
0 |
0 |
0 |
T9 |
18975 |
25 |
0 |
0 |
T20 |
2327 |
49 |
0 |
0 |
T21 |
6505 |
0 |
0 |
0 |
T22 |
4359 |
16 |
0 |
0 |
T23 |
1362 |
0 |
0 |
0 |
T77 |
0 |
18 |
0 |
0 |
T82 |
0 |
45 |
0 |
0 |
T100 |
0 |
57 |
0 |
0 |
T109 |
0 |
36 |
0 |
0 |
T110 |
0 |
73 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148237513 |
0 |
2412 |
T1 |
194166 |
193973 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
3918 |
3903 |
0 |
3 |
T7 |
1639 |
1528 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
1185 |
1167 |
0 |
3 |
T20 |
2352 |
2116 |
0 |
3 |
T21 |
3184 |
3095 |
0 |
3 |
T22 |
1089 |
1018 |
0 |
3 |
T23 |
1311 |
1224 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
17089 |
0 |
0 |
T1 |
194166 |
0 |
0 |
0 |
T3 |
0 |
228 |
0 |
0 |
T4 |
69596 |
0 |
0 |
0 |
T6 |
3918 |
0 |
0 |
0 |
T7 |
1639 |
3 |
0 |
0 |
T8 |
1489 |
0 |
0 |
0 |
T9 |
1185 |
25 |
0 |
0 |
T20 |
2352 |
44 |
0 |
0 |
T21 |
3184 |
0 |
0 |
0 |
T22 |
1089 |
9 |
0 |
0 |
T23 |
1311 |
0 |
0 |
0 |
T77 |
0 |
11 |
0 |
0 |
T82 |
0 |
40 |
0 |
0 |
T100 |
0 |
28 |
0 |
0 |
T109 |
0 |
29 |
0 |
0 |
T110 |
0 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T9,T20 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T9,T20 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148237513 |
0 |
2412 |
T1 |
194166 |
193973 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
3918 |
3903 |
0 |
3 |
T7 |
1639 |
1528 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
1185 |
1167 |
0 |
3 |
T20 |
2352 |
2116 |
0 |
3 |
T21 |
3184 |
3095 |
0 |
3 |
T22 |
1089 |
1018 |
0 |
3 |
T23 |
1311 |
1224 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
19319 |
0 |
0 |
T1 |
194166 |
0 |
0 |
0 |
T3 |
0 |
286 |
0 |
0 |
T4 |
69596 |
0 |
0 |
0 |
T6 |
3918 |
0 |
0 |
0 |
T7 |
1639 |
17 |
0 |
0 |
T8 |
1489 |
0 |
0 |
0 |
T9 |
1185 |
23 |
0 |
0 |
T20 |
2352 |
66 |
0 |
0 |
T21 |
3184 |
0 |
0 |
0 |
T22 |
1089 |
9 |
0 |
0 |
T23 |
1311 |
0 |
0 |
0 |
T77 |
0 |
15 |
0 |
0 |
T82 |
0 |
40 |
0 |
0 |
T100 |
0 |
39 |
0 |
0 |
T109 |
0 |
20 |
0 |
0 |
T110 |
0 |
37 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
386485971 |
0 |
0 |
T1 |
202264 |
202209 |
0 |
0 |
T4 |
69596 |
33980 |
0 |
0 |
T6 |
55969 |
55857 |
0 |
0 |
T7 |
1689 |
1649 |
0 |
0 |
T8 |
1489 |
1391 |
0 |
0 |
T9 |
19766 |
19626 |
0 |
0 |
T20 |
2424 |
2298 |
0 |
0 |
T21 |
6777 |
6636 |
0 |
0 |
T22 |
4541 |
4400 |
0 |
0 |
T23 |
1459 |
1433 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
386485971 |
0 |
0 |
T1 |
202264 |
202209 |
0 |
0 |
T4 |
69596 |
33980 |
0 |
0 |
T6 |
55969 |
55857 |
0 |
0 |
T7 |
1689 |
1649 |
0 |
0 |
T8 |
1489 |
1391 |
0 |
0 |
T9 |
19766 |
19626 |
0 |
0 |
T20 |
2424 |
2298 |
0 |
0 |
T21 |
6777 |
6636 |
0 |
0 |
T22 |
4541 |
4400 |
0 |
0 |
T23 |
1459 |
1433 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
364424552 |
362177192 |
0 |
0 |
T1 |
194166 |
194114 |
0 |
0 |
T4 |
66810 |
32610 |
0 |
0 |
T6 |
53728 |
53621 |
0 |
0 |
T7 |
1622 |
1583 |
0 |
0 |
T8 |
1429 |
1336 |
0 |
0 |
T9 |
18975 |
18840 |
0 |
0 |
T20 |
2327 |
2206 |
0 |
0 |
T21 |
6505 |
6370 |
0 |
0 |
T22 |
4359 |
4224 |
0 |
0 |
T23 |
1362 |
1337 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
364424552 |
362177192 |
0 |
0 |
T1 |
194166 |
194114 |
0 |
0 |
T4 |
66810 |
32610 |
0 |
0 |
T6 |
53728 |
53621 |
0 |
0 |
T7 |
1622 |
1583 |
0 |
0 |
T8 |
1429 |
1336 |
0 |
0 |
T9 |
18975 |
18840 |
0 |
0 |
T20 |
2327 |
2206 |
0 |
0 |
T21 |
6505 |
6370 |
0 |
0 |
T22 |
4359 |
4224 |
0 |
0 |
T23 |
1362 |
1337 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
181346174 |
181346174 |
0 |
0 |
T1 |
97057 |
97057 |
0 |
0 |
T4 |
16309 |
16309 |
0 |
0 |
T6 |
26811 |
26811 |
0 |
0 |
T7 |
818 |
818 |
0 |
0 |
T8 |
668 |
668 |
0 |
0 |
T9 |
11185 |
11185 |
0 |
0 |
T20 |
1289 |
1289 |
0 |
0 |
T21 |
3185 |
3185 |
0 |
0 |
T22 |
2283 |
2283 |
0 |
0 |
T23 |
669 |
669 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
181346174 |
181346174 |
0 |
0 |
T1 |
97057 |
97057 |
0 |
0 |
T4 |
16309 |
16309 |
0 |
0 |
T6 |
26811 |
26811 |
0 |
0 |
T7 |
818 |
818 |
0 |
0 |
T8 |
668 |
668 |
0 |
0 |
T9 |
11185 |
11185 |
0 |
0 |
T20 |
1289 |
1289 |
0 |
0 |
T21 |
3185 |
3185 |
0 |
0 |
T22 |
2283 |
2283 |
0 |
0 |
T23 |
669 |
669 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
90672471 |
90672471 |
0 |
0 |
T1 |
48529 |
48529 |
0 |
0 |
T4 |
8153 |
8153 |
0 |
0 |
T6 |
13405 |
13405 |
0 |
0 |
T7 |
409 |
409 |
0 |
0 |
T8 |
334 |
334 |
0 |
0 |
T9 |
5592 |
5592 |
0 |
0 |
T20 |
644 |
644 |
0 |
0 |
T21 |
1593 |
1593 |
0 |
0 |
T22 |
1141 |
1141 |
0 |
0 |
T23 |
334 |
334 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
90672471 |
90672471 |
0 |
0 |
T1 |
48529 |
48529 |
0 |
0 |
T4 |
8153 |
8153 |
0 |
0 |
T6 |
13405 |
13405 |
0 |
0 |
T7 |
409 |
409 |
0 |
0 |
T8 |
334 |
334 |
0 |
0 |
T9 |
5592 |
5592 |
0 |
0 |
T20 |
644 |
644 |
0 |
0 |
T21 |
1593 |
1593 |
0 |
0 |
T22 |
1141 |
1141 |
0 |
0 |
T23 |
334 |
334 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
186689589 |
185558074 |
0 |
0 |
T1 |
97088 |
97062 |
0 |
0 |
T4 |
33406 |
16306 |
0 |
0 |
T6 |
26865 |
26812 |
0 |
0 |
T7 |
811 |
791 |
0 |
0 |
T8 |
715 |
668 |
0 |
0 |
T9 |
9487 |
9420 |
0 |
0 |
T20 |
1163 |
1103 |
0 |
0 |
T21 |
3253 |
3186 |
0 |
0 |
T22 |
2179 |
2112 |
0 |
0 |
T23 |
692 |
680 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
186689589 |
185558074 |
0 |
0 |
T1 |
97088 |
97062 |
0 |
0 |
T4 |
33406 |
16306 |
0 |
0 |
T6 |
26865 |
26812 |
0 |
0 |
T7 |
811 |
791 |
0 |
0 |
T8 |
715 |
668 |
0 |
0 |
T9 |
9487 |
9420 |
0 |
0 |
T20 |
1163 |
1103 |
0 |
0 |
T21 |
3253 |
3186 |
0 |
0 |
T22 |
2179 |
2112 |
0 |
0 |
T23 |
692 |
680 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148237513 |
0 |
2412 |
T1 |
194166 |
193973 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
3918 |
3903 |
0 |
3 |
T7 |
1639 |
1528 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
1185 |
1167 |
0 |
3 |
T20 |
2352 |
2116 |
0 |
3 |
T21 |
3184 |
3095 |
0 |
3 |
T22 |
1089 |
1018 |
0 |
3 |
T23 |
1311 |
1224 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148237513 |
0 |
2412 |
T1 |
194166 |
193973 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
3918 |
3903 |
0 |
3 |
T7 |
1639 |
1528 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
1185 |
1167 |
0 |
3 |
T20 |
2352 |
2116 |
0 |
3 |
T21 |
3184 |
3095 |
0 |
3 |
T22 |
1089 |
1018 |
0 |
3 |
T23 |
1311 |
1224 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148237513 |
0 |
2412 |
T1 |
194166 |
193973 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
3918 |
3903 |
0 |
3 |
T7 |
1639 |
1528 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
1185 |
1167 |
0 |
3 |
T20 |
2352 |
2116 |
0 |
3 |
T21 |
3184 |
3095 |
0 |
3 |
T22 |
1089 |
1018 |
0 |
3 |
T23 |
1311 |
1224 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148237513 |
0 |
2412 |
T1 |
194166 |
193973 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
3918 |
3903 |
0 |
3 |
T7 |
1639 |
1528 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
1185 |
1167 |
0 |
3 |
T20 |
2352 |
2116 |
0 |
3 |
T21 |
3184 |
3095 |
0 |
3 |
T22 |
1089 |
1018 |
0 |
3 |
T23 |
1311 |
1224 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148237513 |
0 |
2412 |
T1 |
194166 |
193973 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
3918 |
3903 |
0 |
3 |
T7 |
1639 |
1528 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
1185 |
1167 |
0 |
3 |
T20 |
2352 |
2116 |
0 |
3 |
T21 |
3184 |
3095 |
0 |
3 |
T22 |
1089 |
1018 |
0 |
3 |
T23 |
1311 |
1224 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148237513 |
0 |
2412 |
T1 |
194166 |
193973 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
3918 |
3903 |
0 |
3 |
T7 |
1639 |
1528 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
1185 |
1167 |
0 |
3 |
T20 |
2352 |
2116 |
0 |
3 |
T21 |
3184 |
3095 |
0 |
3 |
T22 |
1089 |
1018 |
0 |
3 |
T23 |
1311 |
1224 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151236835 |
148244511 |
0 |
0 |
T1 |
194166 |
193976 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
3918 |
3906 |
0 |
0 |
T7 |
1639 |
1531 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
1185 |
1170 |
0 |
0 |
T20 |
2352 |
2119 |
0 |
0 |
T21 |
3184 |
3098 |
0 |
0 |
T22 |
1089 |
1021 |
0 |
0 |
T23 |
1311 |
1227 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384136580 |
0 |
2412 |
T1 |
202264 |
202063 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
55969 |
55797 |
0 |
3 |
T7 |
1689 |
1574 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
19766 |
19508 |
0 |
3 |
T20 |
2424 |
2181 |
0 |
3 |
T21 |
6777 |
6591 |
0 |
3 |
T22 |
4541 |
4254 |
0 |
3 |
T23 |
1459 |
1359 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
32562 |
0 |
0 |
T1 |
202264 |
26 |
0 |
0 |
T4 |
69596 |
11 |
0 |
0 |
T6 |
55969 |
1 |
0 |
0 |
T7 |
1689 |
12 |
0 |
0 |
T8 |
1489 |
2 |
0 |
0 |
T9 |
19766 |
9 |
0 |
0 |
T20 |
2424 |
16 |
0 |
0 |
T21 |
6777 |
27 |
0 |
0 |
T22 |
4541 |
3 |
0 |
0 |
T23 |
1459 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384136580 |
0 |
2412 |
T1 |
202264 |
202063 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
55969 |
55797 |
0 |
3 |
T7 |
1689 |
1574 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
19766 |
19508 |
0 |
3 |
T20 |
2424 |
2181 |
0 |
3 |
T21 |
6777 |
6591 |
0 |
3 |
T22 |
4541 |
4254 |
0 |
3 |
T23 |
1459 |
1359 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
32204 |
0 |
0 |
T1 |
202264 |
26 |
0 |
0 |
T4 |
69596 |
11 |
0 |
0 |
T6 |
55969 |
1 |
0 |
0 |
T7 |
1689 |
10 |
0 |
0 |
T8 |
1489 |
1 |
0 |
0 |
T9 |
19766 |
9 |
0 |
0 |
T20 |
2424 |
21 |
0 |
0 |
T21 |
6777 |
20 |
0 |
0 |
T22 |
4541 |
7 |
0 |
0 |
T23 |
1459 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384136580 |
0 |
2412 |
T1 |
202264 |
202063 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
55969 |
55797 |
0 |
3 |
T7 |
1689 |
1574 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
19766 |
19508 |
0 |
3 |
T20 |
2424 |
2181 |
0 |
3 |
T21 |
6777 |
6591 |
0 |
3 |
T22 |
4541 |
4254 |
0 |
3 |
T23 |
1459 |
1359 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
32304 |
0 |
0 |
T1 |
202264 |
18 |
0 |
0 |
T4 |
69596 |
11 |
0 |
0 |
T6 |
55969 |
1 |
0 |
0 |
T7 |
1689 |
16 |
0 |
0 |
T8 |
1489 |
1 |
0 |
0 |
T9 |
19766 |
11 |
0 |
0 |
T20 |
2424 |
20 |
0 |
0 |
T21 |
6777 |
23 |
0 |
0 |
T22 |
4541 |
7 |
0 |
0 |
T23 |
1459 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384136580 |
0 |
2412 |
T1 |
202264 |
202063 |
0 |
3 |
T4 |
69596 |
5366 |
0 |
3 |
T6 |
55969 |
55797 |
0 |
3 |
T7 |
1689 |
1574 |
0 |
3 |
T8 |
1489 |
1345 |
0 |
3 |
T9 |
19766 |
19508 |
0 |
3 |
T20 |
2424 |
2181 |
0 |
3 |
T21 |
6777 |
6591 |
0 |
3 |
T22 |
4541 |
4254 |
0 |
3 |
T23 |
1459 |
1359 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
32578 |
0 |
0 |
T1 |
202264 |
22 |
0 |
0 |
T4 |
69596 |
11 |
0 |
0 |
T6 |
55969 |
1 |
0 |
0 |
T7 |
1689 |
12 |
0 |
0 |
T8 |
1489 |
2 |
0 |
0 |
T9 |
19766 |
9 |
0 |
0 |
T20 |
2424 |
18 |
0 |
0 |
T21 |
6777 |
12 |
0 |
0 |
T22 |
4541 |
7 |
0 |
0 |
T23 |
1459 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
388844616 |
384143487 |
0 |
0 |
T1 |
202264 |
202066 |
0 |
0 |
T4 |
69596 |
5409 |
0 |
0 |
T6 |
55969 |
55800 |
0 |
0 |
T7 |
1689 |
1577 |
0 |
0 |
T8 |
1489 |
1348 |
0 |
0 |
T9 |
19766 |
19511 |
0 |
0 |
T20 |
2424 |
2184 |
0 |
0 |
T21 |
6777 |
6594 |
0 |
0 |
T22 |
4541 |
4257 |
0 |
0 |
T23 |
1459 |
1362 |
0 |
0 |