Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T5,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	151236835	148113744	0	0
AllClkBypReqTrue_A	151236835	128492	0	0
IoClkBypReqFalse_A	151236835	148028677	0	2412
IoClkBypReqTrue_A	151236835	209009	0	0
LcClkBypAckFalse_A	151236835	148118022	0	0
LcClkBypAckTrue_A	151236835	124214	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	148113744	0	0
T1	194166	193975	0	0
T4	69596	5398	0	0
T6	3918	3905	0	0
T7	1639	1475	0	0
T8	1489	1347	0	0
T9	1185	1034	0	0
T20	2352	1800	0	0
T21	3184	3097	0	0
T22	1089	986	0	0
T23	1311	1226	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	128492	0	0
T1	194166	0	0	0
T3	0	2250	0	0
T4	69596	0	0	0
T6	3918	0	0	0
T7	1639	55	0	0
T8	1489	0	0	0
T9	1185	135	0	0
T20	2352	318	0	0
T21	3184	0	0	0
T22	1089	34	0	0
T23	1311	0	0	0
T77	0	94	0	0
T82	0	260	0	0
T100	0	291	0	0
T109	0	165	0	0
T110	0	138	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	148028677	0	2412
T1	194166	193973	0	3
T4	69596	5376	0	3
T6	3918	3903	0	3
T7	1639	1503	0	3
T8	1489	1345	0	3
T9	1185	958	0	3
T20	2352	1805	0	3
T21	3184	3095	0	3
T22	1089	907	0	3
T23	1311	1224	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	209009	0	0
T1	194166	0	0	0
T3	0	2930	0	0
T4	69596	0	0	0
T6	3918	0	0	0
T7	1639	25	0	0
T8	1489	0	0	0
T9	1185	209	0	0
T20	2352	311	0	0
T21	3184	0	0	0
T22	1089	111	0	0
T23	1311	0	0	0
T77	0	102	0	0
T82	0	393	0	0
T100	0	339	0	0
T109	0	409	0	0
T110	0	211	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	148118022	0	0
T1	194166	193975	0	0
T4	69596	5398	0	0
T6	3918	3905	0	0
T7	1639	1509	0	0
T8	1489	1347	0	0
T9	1185	1060	0	0
T20	2352	1943	0	0
T21	3184	3097	0	0
T22	1089	952	0	0
T23	1311	1226	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	124214	0	0
T1	194166	0	0	0
T3	0	2037	0	0
T4	69596	0	0	0
T6	3918	0	0	0
T7	1639	21	0	0
T8	1489	0	0	0
T9	1185	109	0	0
T20	2352	175	0	0
T21	3184	0	0	0
T22	1089	68	0	0
T23	1311	0	0	0
T77	0	23	0	0
T82	0	213	0	0
T100	0	192	0	0
T109	0	261	0	0
T110	0	80	0	0