Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1555380152	15627	0	0
TransStop_A	1555380152	8069	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555380152	15627	0	0
T2	0	11	0	0
T3	0	456	0	0
T4	278388	0	0	0
T5	447976	0	0	0
T14	0	46	0	0
T21	27108	21	0	0
T22	18168	0	0	0
T23	5836	0	0	0
T24	559756	0	0	0
T25	14836	19	0	0
T29	0	83	0	0
T37	33504	27	0	0
T78	0	37	0	0
T80	0	3	0	0
T100	17900	0	0	0
T109	14592	0	0	0
T111	0	2	0	0
T112	0	29	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555380152	8069	0	0
T3	0	193	0	0
T4	278388	0	0	0
T5	447976	0	0	0
T14	0	28	0	0
T21	27108	8	0	0
T22	18168	0	0	0
T23	5836	0	0	0
T24	559756	0	0	0
T25	14836	11	0	0
T29	0	47	0	0
T37	33504	14	0	0
T78	0	18	0	0
T80	0	2	0	0
T100	17900	0	0	0
T109	14592	0	0	0
T111	0	2	0	0
T112	0	15	0	0
T113	0	3	0	0
T114	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	388845038	3914	0	0
TransStop_A	388845038	2040	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388845038	3914	0	0
T2	0	2	0	0
T3	0	119	0	0
T4	69597	0	0	0
T5	111994	0	0	0
T14	0	18	0	0
T21	6777	5	0	0
T22	4542	0	0	0
T23	1459	0	0	0
T24	139939	0	0	0
T25	3709	6	0	0
T29	0	22	0	0
T37	8376	9	0	0
T78	0	8	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T112	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388845038	2040	0	0
T3	0	57	0	0
T4	69597	0	0	0
T5	111994	0	0	0
T14	0	8	0	0
T21	6777	2	0	0
T22	4542	0	0	0
T23	1459	0	0	0
T24	139939	0	0	0
T25	3709	3	0	0
T29	0	14	0	0
T37	8376	5	0	0
T78	0	3	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T112	0	4	0	0
T113	0	1	0	0
T114	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	388845038	3924	0	0
TransStop_A	388845038	2052	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388845038	3924	0	0
T2	0	3	0	0
T3	0	115	0	0
T4	69597	0	0	0
T5	111994	0	0	0
T21	6777	5	0	0
T22	4542	0	0	0
T23	1459	0	0	0
T24	139939	0	0	0
T25	3709	3	0	0
T29	0	22	0	0
T37	8376	5	0	0
T78	0	11	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T111	0	1	0	0
T112	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388845038	2052	0	0
T3	0	48	0	0
T4	69597	0	0	0
T5	111994	0	0	0
T14	0	5	0	0
T21	6777	3	0	0
T22	4542	0	0	0
T23	1459	0	0	0
T24	139939	0	0	0
T25	3709	2	0	0
T29	0	13	0	0
T37	8376	3	0	0
T78	0	7	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T111	0	1	0	0
T112	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	388845038	3881	0	0
TransStop_A	388845038	1984	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388845038	3881	0	0
T2	0	4	0	0
T3	0	107	0	0
T4	69597	0	0	0
T5	111994	0	0	0
T14	0	15	0	0
T21	6777	4	0	0
T22	4542	0	0	0
T23	1459	0	0	0
T24	139939	0	0	0
T25	3709	5	0	0
T29	0	15	0	0
T37	8376	5	0	0
T78	0	8	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T111	0	1	0	0
T112	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388845038	1984	0	0
T3	0	42	0	0
T4	69597	0	0	0
T5	111994	0	0	0
T14	0	7	0	0
T21	6777	1	0	0
T22	4542	0	0	0
T23	1459	0	0	0
T24	139939	0	0	0
T25	3709	2	0	0
T29	0	9	0	0
T37	8376	3	0	0
T78	0	2	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T111	0	1	0	0
T112	0	3	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	388845038	3908	0	0
TransStop_A	388845038	1993	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388845038	3908	0	0
T2	0	2	0	0
T3	0	115	0	0
T4	69597	0	0	0
T5	111994	0	0	0
T14	0	13	0	0
T21	6777	7	0	0
T22	4542	0	0	0
T23	1459	0	0	0
T24	139939	0	0	0
T25	3709	5	0	0
T29	0	24	0	0
T37	8376	8	0	0
T78	0	10	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T112	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388845038	1993	0	0
T3	0	46	0	0
T4	69597	0	0	0
T5	111994	0	0	0
T14	0	8	0	0
T21	6777	2	0	0
T22	4542	0	0	0
T23	1459	0	0	0
T24	139939	0	0	0
T25	3709	4	0	0
T29	0	11	0	0
T37	8376	3	0	0
T78	0	6	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T112	0	3	0	0
T113	0	1	0	0