Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	849843	0	0
SrcPulseCheck_M	2147483647	846084	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	849843
T1	930296	430
T2	0	394
T3	0	7068
T4	263082	100
T5	369960	160
T6	207453	137
T13	0	386
T14	0	1808
T15	0	361
T20	11614	0
T21	27614	0
T22	17979	0
T23	6473	0
T24	542807	536
T25	15247	0
T26	0	176
T29	0	940
T30	0	180
T62	7992	1
T63	6065	0
T64	19880	2
T66	4194	1
T67	9492	1
T69	19236	2
T83	0	1
T119	3710	1
T120	7790	1
T121	17950	0
T122	34960	0
T123	20306	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	846084
T1	487593	430
T2	0	394
T3	0	6591
T4	156121	100
T5	120746	160
T6	35263	137
T13	0	386
T14	0	1808
T15	0	361
T20	6673	0
T21	11449	0
T22	5729	0
T23	3715	0
T24	336833	536
T25	6556	0
T26	0	176
T29	0	940
T30	0	180
T62	13722	1
T63	2569	0
T64	8518	2
T66	10604	1
T67	3870	1
T69	7732	2
T83	0	1
T119	8465	1
T120	14830	1
T121	33904	0
T122	16608	0
T123	17390	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	6	75.00
Logical	8	6	75.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T62,T65
1	0	Covered	T61,T62,T65
1	1	Not Covered

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T62,T65
1	0	Not Covered
1	1	Covered	T61,T62,T65

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	24	0	0
SrcPulseCheck_M	367044502	24	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	24
T61	4040	1
T62	3996	2
T64	9940	2
T65	5841	3
T69	9618	1
T120	3895	1
T121	8975	1
T123	10153	1
T124	6093	1
T125	7538	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	367044502	24
T61	16159	1
T62	14754	2
T64	9940	2
T65	16992	3
T69	9618	1
T120	15579	1
T121	35900	1
T123	19892	1
T124	12445	1
T125	7236	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	6	75.00
Logical	8	6	75.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T62,T65
1	0	Covered	T61,T62,T65
1	1	Not Covered

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T62,T65
1	0	Not Covered
1	1	Covered	T61,T62,T65

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	21	0	0
SrcPulseCheck_M	367044502	21	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	21
T61	4040	1
T62	3996	1
T64	9940	1
T65	5841	4
T120	3895	2
T121	8975	1
T125	7538	1
T126	4404	1
T127	8033	1
T128	6635	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	367044502	21
T61	16159	1
T62	14754	1
T64	9940	1
T65	16992	4
T120	15579	2
T121	35900	1
T125	7236	1
T126	12434	1
T127	7711	1
T128	25478	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	367044502	23071	0	0
SrcPulseCheck_M	152171262	23071	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	367044502	23071
T1	194166	34
T2	0	26
T3	0	377
T4	66810	20
T5	107511	32
T6	53728	8
T13	0	30
T20	2327	0
T21	6505	0
T22	4359	0
T23	1362	0
T24	94019	24
T25	3559	0
T29	0	32
T30	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	23071
T1	194166	34
T2	0	26
T3	0	377
T4	69596	20
T5	44797	32
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	367044502	28997	0	0
SrcPulseCheck_M	152171262	29011	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	367044502	28997
T1	194166	34
T2	0	26
T3	0	389
T4	66810	40
T5	107511	64
T6	53728	8
T13	0	30
T20	2327	0
T21	6505	0
T22	4359	0
T23	1362	0
T24	94019	24
T25	3559	0
T29	0	32
T30	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	29011
T1	194166	34
T2	0	26
T3	0	389
T4	69596	40
T5	44797	64
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	28989	0	0
SrcPulseCheck_M	367044502	29000	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	28989
T1	194166	34
T2	0	26
T3	0	389
T4	69596	40
T5	44797	64
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	367044502	29000
T1	194166	34
T2	0	26
T3	0	389
T4	66810	40
T5	107511	64
T6	53728	8
T13	0	30
T20	2327	0
T21	6505	0
T22	4359	0
T23	1362	0
T24	94019	24
T25	3559	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	182612218	23071	0	0
SrcPulseCheck_M	152171262	23071	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	182612218	23071
T1	97057	34
T2	0	26
T3	0	377
T4	16309	20
T5	30188	32
T6	26811	8
T13	0	30
T20	1289	0
T21	3185	0
T22	2283	0
T23	669	0
T24	46963	24
T25	1740	0
T29	0	32
T30	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	23071
T1	194166	34
T2	0	26
T3	0	377
T4	69596	20
T5	44797	32
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	182612218	28936	0	0
SrcPulseCheck_M	152171262	28959	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	182612218	28936
T1	97057	34
T2	0	26
T3	0	389
T4	16309	40
T5	30188	64
T6	26811	8
T13	0	30
T20	1289	0
T21	3185	0
T22	2283	0
T23	669	0
T24	46963	24
T25	1740	0
T29	0	32
T30	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	28959
T1	194166	34
T2	0	26
T3	0	389
T4	69596	40
T5	44797	64
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	28934	0	0
SrcPulseCheck_M	182612218	28937	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	28934
T1	194166	34
T2	0	26
T3	0	389
T4	69596	40
T5	44797	64
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	182612218	28937
T1	97057	34
T2	0	26
T3	0	389
T4	16309	40
T5	30188	64
T6	26811	8
T13	0	30
T20	1289	0
T21	3185	0
T22	2283	0
T23	669	0
T24	46963	24
T25	1740	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	91305474	23071	0	0
SrcPulseCheck_M	152171262	23071	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	91305474	23071
T1	48529	34
T2	0	26
T3	0	377
T4	8153	20
T5	15094	32
T6	13405	8
T13	0	30
T20	644	0
T21	1593	0
T22	1141	0
T23	334	0
T24	23481	24
T25	870	0
T29	0	32
T30	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	23071
T1	194166	34
T2	0	26
T3	0	377
T4	69596	20
T5	44797	32
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	91305474	28910	0	0
SrcPulseCheck_M	152171262	28933	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	91305474	28910
T1	48529	34
T2	0	26
T3	0	389
T4	8153	40
T5	15094	64
T6	13405	8
T13	0	30
T20	644	0
T21	1593	0
T22	1141	0
T23	334	0
T24	23481	24
T25	870	0
T29	0	32
T30	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	28933
T1	194166	34
T2	0	26
T3	0	389
T4	69596	40
T5	44797	64
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	28903	0	0
SrcPulseCheck_M	91305474	28911	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	28903
T1	194166	34
T2	0	26
T3	0	389
T4	69596	40
T5	44797	64
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	91305474	28911
T1	48529	34
T2	0	26
T3	0	389
T4	8153	40
T5	15094	64
T6	13405	8
T13	0	30
T20	644	0
T21	1593	0
T22	1141	0
T23	334	0
T24	23481	24
T25	870	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	391573830	23071	0	0
SrcPulseCheck_M	152171262	23071	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	391573830	23071
T1	202264	34
T2	0	26
T3	0	377
T4	69596	20
T5	111994	32
T6	55969	8
T13	0	30
T20	2424	0
T21	6777	0
T22	4541	0
T23	1459	0
T24	139939	24
T25	3708	0
T29	0	32
T30	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	23071
T1	194166	34
T2	0	26
T3	0	377
T4	69596	20
T5	44797	32
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	36

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	391573830	29024	0	0
SrcPulseCheck_M	152171262	29034	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	391573830	29024
T1	202264	34
T2	0	26
T3	0	389
T4	69596	40
T5	111994	64
T6	55969	8
T13	0	30
T20	2424	0
T21	6777	0
T22	4541	0
T23	1459	0
T24	139939	24
T25	3708	0
T29	0	32
T30	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	29034
T1	194166	34
T2	0	26
T3	0	389
T4	69596	40
T5	44797	64
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	29015	0	0
SrcPulseCheck_M	391573830	29026	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	29015
T1	194166	34
T2	0	26
T3	0	389
T4	69596	40
T5	44797	64
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	391573830	29026
T1	202264	34
T2	0	26
T3	0	389
T4	69596	40
T5	111994	64
T6	55969	8
T13	0	30
T20	2424	0
T21	6777	0
T22	4541	0
T23	1459	0
T24	139939	24
T25	3708	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	187999598	22605	0	0
SrcPulseCheck_M	152171262	23071	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	187999598	22605
T1	97088	34
T2	0	26
T3	0	377
T4	33406	10
T5	53758	16
T6	26865	8
T13	0	30
T20	1163	0
T21	3253	0
T22	2179	0
T23	692	0
T24	64291	24
T25	1779	0
T29	0	32
T30	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	23071
T1	194166	34
T2	0	26
T3	0	377
T4	69596	20
T5	44797	32
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	36

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	187999598	28658	0	0
SrcPulseCheck_M	152171262	28888	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	187999598	28658
T1	97088	34
T2	0	26
T3	0	389
T4	33406	35
T5	53758	63
T6	26865	8
T13	0	30
T20	1163	0
T21	3253	0
T22	2179	0
T23	692	0
T24	64291	24
T25	1779	0
T29	0	32
T30	0	70

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	152171262	28888
T1	194166	34
T2	0	26
T3	0	389
T4	69596	40
T5	44797	64
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	28561	0	0
SrcPulseCheck_M	187999598	28687	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	28561
T1	194166	34
T2	0	26
T3	0	389
T4	69596	35
T5	44797	59
T6	3918	8
T13	0	30
T20	2352	0
T21	3184	0
T22	1089	0
T23	1311	0
T24	144479	24
T25	1890	0
T29	0	32
T30	0	70

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	187999598	28687
T1	97088	34
T2	0	26
T3	0	389
T4	33406	38
T5	53758	64
T6	26865	8
T13	0	30
T20	1163	0
T21	3253	0
T22	2179	0
T23	692	0
T24	64291	24
T25	1779	0
T29	0	32
T30	0	72

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T62,T66,T64
1	0	Covered	T62,T66,T64
1	1	Covered	T69

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T62,T66,T64
1	0	Covered	T69
1	1	Covered	T62,T66,T64

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	24	0	0
SrcPulseCheck_M	182612218	24	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	24
T62	3996	1
T64	9940	2
T66	2097	1
T67	4746	1
T69	9618	2
T119	3710	1
T120	3895	1
T121	8975	3
T122	17480	1
T123	10153	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	182612218	24
T62	6861	1
T64	4259	2
T66	5302	1
T67	1935	1
T69	3866	2
T119	8465	1
T120	7415	1
T121	16952	3
T122	8304	1
T123	8695	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T62,T63,T66
1	0	Covered	T62,T63,T66
1	1	Covered	T62,T63,T69

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T62,T63,T66
1	0	Covered	T62,T63,T69
1	1	Covered	T62,T63,T66

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	29	0	0
SrcPulseCheck_M	182612218	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	29
T62	3996	2
T63	6065	2
T64	9940	1
T66	2097	1
T67	4746	1
T69	9618	3
T120	3895	2
T121	8975	2
T122	17480	1
T123	10153	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	182612218	29
T62	6861	2
T63	2569	2
T64	4259	1
T66	5302	1
T67	1935	1
T69	3866	3
T120	7415	2
T121	16952	2
T122	8304	1
T123	8695	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T66,T65
1	0	Covered	T61,T66,T65
1	1	Covered	T68,T121,T123

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T66,T65
1	0	Covered	T68,T121,T123
1	1	Covered	T61,T66,T65

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	24	0	0
SrcPulseCheck_M	91305474	24	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	24
T61	4040	1
T65	5841	1
T66	2097	1
T68	3409	2
T69	9618	2
T86	4416	1
T120	3895	1
T121	8975	3
T123	10153	3
T129	7001	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	91305474	24
T61	3847	1
T65	3870	1
T66	2651	1
T68	2793	2
T69	1932	2
T86	1946	1
T120	3707	1
T121	8473	3
T123	4348	3
T129	7413	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T64,T68
1	0	Covered	T61,T64,T68
1	1	Covered	T68,T121,T130

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T64,T68
1	0	Covered	T68,T121,T130
1	1	Covered	T61,T64,T68

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	22	0	0
SrcPulseCheck_M	91305474	22	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	22
T61	4040	1
T64	9940	1
T68	3409	3
T69	9618	1
T120	3895	1
T121	8975	3
T123	10153	1
T124	6093	1
T125	7538	1
T131	14017	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	91305474	22
T61	3847	1
T64	2131	1
T68	2793	3
T69	1932	1
T120	3707	1
T121	8473	3
T123	4348	1
T124	2873	1
T125	1635	1
T131	2986	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T62,T63
1	0	Covered	T61,T62,T63
1	1	Covered	T66,T65,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T62,T63
1	0	Covered	T66,T65,T132
1	1	Covered	T61,T62,T63

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	35	0	0
SrcPulseCheck_M	391573830	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	35
T61	4040	2
T62	3996	1
T63	6065	2
T64	9940	1
T65	5841	2
T66	2097	2
T67	4746	1
T68	3409	1
T69	9618	1
T119	3710	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	391573830	35
T61	16833	2
T62	15370	1
T63	6383	2
T64	10355	1
T65	17701	2
T66	11656	2
T67	4842	1
T68	12629	1
T69	10019	1
T119	18554	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T62,T63
1	0	Covered	T61,T62,T63
1	1	Covered	T61,T62,T63

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T61,T62,T63
1	0	Covered	T61,T62,T63
1	1	Covered	T61,T62,T63

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	45	0	0
SrcPulseCheck_M	391573830	45	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	45
T61	4040	3
T62	3996	2
T63	6065	3
T65	5841	2
T66	2097	2
T67	4746	2
T68	3409	2
T69	9618	2
T86	4416	1
T119	3710	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	391573830	45
T61	16833	3
T62	15370	2
T63	6383	3
T65	17701	2
T66	11656	2
T67	4842	2
T68	12629	2
T69	10019	2
T86	9014	1
T119	18554	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T62,T66,T65
1	0	Covered	T62,T66,T65
1	1	Covered	T66,T65,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T62,T66,T65
1	0	Covered	T66,T65,T122
1	1	Covered	T62,T66,T65

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	34	0	0
SrcPulseCheck_M	187999598	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	34
T62	3996	1
T64	9940	1
T65	5841	3
T66	2097	2
T67	4746	3
T69	9618	2
T119	3710	2
T120	3895	1
T122	17480	2
T133	5693	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	187999598	34
T62	7378	1
T64	4971	1
T65	8497	3
T66	5594	2
T67	2324	3
T69	4809	2
T119	8906	2
T120	7790	1
T122	9023	2
T133	7192	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T62,T66,T65
1	0	Covered	T62,T66,T65
1	1	Covered	T66,T134,T135

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T62,T66,T65
1	0	Covered	T66,T134,T135
1	1	Covered	T62,T66,T65

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	152171262	32	0	0
SrcPulseCheck_M	187999598	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	152171262	32
T62	3996	1
T64	9940	1
T65	5841	2
T66	2097	3
T67	4746	1
T69	9618	1
T119	3710	1
T120	3895	1
T121	8975	1
T122	17480	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	187999598	32
T62	7378	1
T64	4971	1
T65	8497	2
T66	5594	3
T67	2324	1
T69	4809	1
T119	8906	1
T120	7790	1
T121	17951	1
T122	9023	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	364424552	83410	0	0
SrcPulseCheck_M	11054676	82062	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	364424552	83410
T1	194166	82
T2	0	79
T3	0	1389
T4	66810	0
T5	107511	0
T6	53728	29
T13	0	74
T14	0	428
T20	2327	0
T21	6505	0
T22	4359	0
T23	1362	0
T24	94019	95
T25	3559	0
T26	0	44
T29	0	214
T83	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	11054676	82062
T1	551	82
T2	0	79
T3	0	1230
T4	155	0
T5	241	0
T6	154	29
T13	0	74
T14	0	428
T20	170	0
T21	474	0
T22	317	0
T23	106	0
T24	207	95
T25	259	0
T26	0	44
T29	0	214
T83	0	1

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	181346174	82810	0	0
SrcPulseCheck_M	11054676	81465	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	181346174	82810
T1	97057	82
T2	0	79
T3	0	1389
T4	16309	0
T5	30188	0
T6	26811	29
T13	0	74
T14	0	428
T15	0	124
T20	1289	0
T21	3185	0
T22	2283	0
T23	669	0
T24	46963	95
T25	1740	0
T26	0	44
T29	0	214

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	11054676	81465
T1	551	82
T2	0	79
T3	0	1230
T4	155	0
T5	241	0
T6	154	29
T13	0	74
T14	0	428
T15	0	124
T20	170	0
T21	474	0
T22	317	0
T23	106	0
T24	207	95
T25	259	0
T26	0	44
T29	0	214

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	90672471	81947	0	0
SrcPulseCheck_M	11054676	80608	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	90672471	81947
T1	48529	82
T2	0	79
T3	0	1389
T4	8153	0
T5	15094	0
T6	13405	29
T13	0	74
T14	0	428
T15	0	124
T20	644	0
T21	1593	0
T22	1141	0
T23	334	0
T24	23481	95
T25	870	0
T26	0	44
T29	0	214

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	11054676	80608
T1	551	82
T2	0	79
T3	0	1230
T4	155	0
T5	241	0
T6	154	29
T13	0	74
T14	0	428
T15	0	124
T20	170	0
T21	474	0
T22	317	0
T23	106	0
T24	207	95
T25	259	0
T26	0	44
T29	0	214

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	388844616	99222	0	0
SrcPulseCheck_M	11578043	98943	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	388844616	99222
T1	202264	82
T2	0	79
T3	0	1746
T4	69596	0
T5	111994	0
T6	55969	26
T13	0	74
T14	0	524
T15	0	113
T20	2424	0
T21	6777	0
T22	4541	0
T23	1459	0
T24	139939	179
T25	3708	0
T26	0	44
T29	0	202

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	11578043	98943
T1	551	82
T2	0	79
T3	0	1746
T4	155	0
T5	241	0
T6	154	26
T13	0	74
T14	0	524
T15	0	113
T20	170	0
T21	474	0
T22	317	0
T23	106	0
T24	291	179
T25	259	0
T26	0	44
T29	0	202

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T6,T24
1	0	Covered	T1,T6,T24
1	1	Covered	T1,T6,T24

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	186689589	98348	0	0
SrcPulseCheck_M	11576219	97975	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	186689589	98348
T1	97088	82
T2	0	69
T3	0	1765
T4	33406	0
T5	53758	0
T6	26865	25
T13	0	74
T14	0	548
T15	0	108
T20	1163	0
T21	3253	0
T22	2179	0
T23	692	0
T24	64291	167
T25	1779	0
T26	0	44
T29	0	214

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	11576219	97975
T1	551	82
T2	0	69
T3	0	1765
T4	155	0
T5	241	0
T6	154	25
T13	0	74
T14	0	548
T15	0	108
T20	170	0
T21	474	0
T22	317	0
T23	106	0
T24	279	167
T25	259	0
T26	0	44
T29	0	214

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00