Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	152171262	4777004	0	0
clk_enables_rd_A	152171262	35857	0	0
clk_hints_rd_A	152171262	31461	0	0
extclk_ctrl_rd_A	152171262	41401	0	0
extclk_ctrl_regwen_rd_A	152171262	30576	0	0
jitter_enable_rd_A	152171262	48237	0	0
jitter_regwen_rd_A	152171262	34174	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152171262	4777004	0	0
T3	480425	163099	0	0
T13	172049	0	0	0
T17	0	162739	0	0
T19	0	85016	0	0
T28	0	135507	0	0
T29	206910	0	0	0
T34	0	192508	0	0
T70	0	84331	0	0
T71	0	70809	0	0
T72	0	70769	0	0
T73	0	167662	0	0
T74	0	98270	0	0
T75	1827	0	0	0
T76	829	0	0	0
T77	1021	0	0	0
T78	2445	0	0	0
T79	1341	0	0	0
T80	1108	0	0	0
T81	1686	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152171262	35857	0	0
T72	206662	0	0	0
T116	203476	0	0	0
T136	549312	11	0	0
T137	0	4	0	0
T138	0	2	0	0
T139	0	1574	0	0
T140	0	9	0	0
T141	0	10	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	7	0	0
T145	0	4	0	0
T146	1497	0	0	0
T147	1453	0	0	0
T148	1359	0	0	0
T149	859	0	0	0
T150	1751	0	0	0
T151	1233	0	0	0
T152	1103	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152171262	31461	0	0
T14	967290	4	0	0
T15	56524	0	0	0
T16	665469	0	0	0
T32	1749	0	0	0
T92	1779	0	0	0
T113	2169	0	0	0
T114	2484	0	0	0
T136	0	17	0	0
T137	0	3	0	0
T138	0	2	0	0
T139	0	965	0	0
T141	0	9	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	8	0	0
T153	0	7	0	0
T154	964	0	0	0
T155	2909	0	0	0
T156	2292	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152171262	41401	0	0
T1	194166	0	0	0
T4	69596	0	0	0
T6	3918	0	0	0
T9	1185	37	0	0
T14	0	60	0	0
T16	0	211	0	0
T20	2352	0	0	0
T21	3184	0	0	0
T22	1089	0	0	0
T23	1311	0	0	0
T24	144479	0	0	0
T25	1890	0	0	0
T30	0	146	0	0
T81	0	19	0	0
T82	0	41	0	0
T83	0	64	0	0
T92	0	34	0	0
T93	0	38	0	0
T109	0	27	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152171262	30576	0	0
T14	967290	0	0	0
T15	56524	0	0	0
T26	38743	0	0	0
T30	111735	63	0	0
T83	24229	35	0	0
T111	1327	0	0	0
T112	2307	0	0	0
T113	2169	0	0	0
T139	0	1323	0	0
T157	0	90	0	0
T158	0	44	0	0
T159	0	46	0	0
T160	0	69	0	0
T161	0	29	0	0
T162	0	34	0	0
T163	0	48	0	0
T164	2203	0	0	0
T165	657	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152171262	48237	0	0
T14	967290	132	0	0
T15	56524	0	0	0
T16	665469	0	0	0
T32	1749	0	0	0
T92	1779	0	0	0
T113	2169	0	0	0
T114	2484	0	0	0
T136	0	682	0	0
T137	0	239	0	0
T138	0	119	0	0
T139	0	2064	0	0
T140	0	64	0	0
T141	0	250	0	0
T142	0	124	0	0
T143	0	207	0	0
T153	0	143	0	0
T154	964	0	0	0
T155	2909	0	0	0
T156	2292	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152171262	34174	0	0
T36	0	2888	0	0
T139	126503	1450	0	0
T140	1988	0	0	0
T163	90632	0	0	0
T166	0	4155	0	0
T167	0	3278	0	0
T168	0	1965	0	0
T169	0	2161	0	0
T170	0	826	0	0
T171	0	1723	0	0
T172	0	3261	0	0
T173	0	1740	0	0
T174	1240	0	0	0
T175	2155	0	0	0
T176	417696	0	0	0
T177	1070	0	0	0
T178	2777	0	0	0
T179	1106	0	0	0
T180	184724	0	0	0