SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T9,T1 |
1 | 0 | Covered | T7,T9,T20 |
1 | 1 | Covered | T7,T9,T20 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 364425001 | 4425 | 0 | 0 |
g_div2.Div2Whole_A | 364425001 | 5268 | 0 | 0 |
g_div4.Div4Stepped_A | 181346572 | 4325 | 0 | 0 |
g_div4.Div4Whole_A | 181346572 | 4938 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 364425001 | 4425 | 0 | 0 |
T1 | 194167 | 0 | 0 | 0 |
T3 | 0 | 60 | 0 | 0 |
T4 | 66811 | 0 | 0 | 0 |
T6 | 53729 | 0 | 0 | 0 |
T7 | 1622 | 1 | 0 | 0 |
T8 | 1430 | 0 | 0 | 0 |
T9 | 18975 | 4 | 0 | 0 |
T20 | 2327 | 9 | 0 | 0 |
T21 | 6506 | 0 | 0 | 0 |
T22 | 4360 | 3 | 0 | 0 |
T23 | 1362 | 0 | 0 | 0 |
T77 | 0 | 2 | 0 | 0 |
T82 | 0 | 6 | 0 | 0 |
T100 | 0 | 9 | 0 | 0 |
T109 | 0 | 7 | 0 | 0 |
T110 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 364425001 | 5268 | 0 | 0 |
T1 | 194167 | 0 | 0 | 0 |
T3 | 0 | 71 | 0 | 0 |
T4 | 66811 | 0 | 0 | 0 |
T6 | 53729 | 0 | 0 | 0 |
T7 | 1622 | 3 | 0 | 0 |
T8 | 1430 | 0 | 0 | 0 |
T9 | 18975 | 4 | 0 | 0 |
T20 | 2327 | 12 | 0 | 0 |
T21 | 6506 | 0 | 0 | 0 |
T22 | 4360 | 3 | 0 | 0 |
T23 | 1362 | 0 | 0 | 0 |
T77 | 0 | 2 | 0 | 0 |
T82 | 0 | 7 | 0 | 0 |
T100 | 0 | 10 | 0 | 0 |
T109 | 0 | 8 | 0 | 0 |
T110 | 0 | 9 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 181346572 | 4325 | 0 | 0 |
T1 | 97058 | 0 | 0 | 0 |
T3 | 0 | 58 | 0 | 0 |
T4 | 16310 | 0 | 0 | 0 |
T6 | 26811 | 0 | 0 | 0 |
T7 | 818 | 1 | 0 | 0 |
T8 | 669 | 0 | 0 | 0 |
T9 | 11186 | 4 | 0 | 0 |
T20 | 1290 | 9 | 0 | 0 |
T21 | 3186 | 0 | 0 | 0 |
T22 | 2284 | 3 | 0 | 0 |
T23 | 669 | 0 | 0 | 0 |
T77 | 0 | 2 | 0 | 0 |
T82 | 0 | 6 | 0 | 0 |
T100 | 0 | 9 | 0 | 0 |
T109 | 0 | 7 | 0 | 0 |
T110 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 181346572 | 4938 | 0 | 0 |
T1 | 97058 | 0 | 0 | 0 |
T3 | 0 | 63 | 0 | 0 |
T4 | 16310 | 0 | 0 | 0 |
T6 | 26811 | 0 | 0 | 0 |
T7 | 818 | 3 | 0 | 0 |
T8 | 669 | 0 | 0 | 0 |
T9 | 11186 | 4 | 0 | 0 |
T20 | 1290 | 8 | 0 | 0 |
T21 | 3186 | 0 | 0 | 0 |
T22 | 2284 | 3 | 0 | 0 |
T23 | 669 | 0 | 0 | 0 |
T77 | 0 | 2 | 0 | 0 |
T82 | 0 | 7 | 0 | 0 |
T100 | 0 | 10 | 0 | 0 |
T109 | 0 | 8 | 0 | 0 |
T110 | 0 | 9 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T9,T1 |
1 | 0 | Covered | T7,T9,T20 |
1 | 1 | Covered | T7,T9,T20 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 364425001 | 4425 | 0 | 0 |
g_div2.Div2Whole_A | 364425001 | 5268 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 364425001 | 4425 | 0 | 0 |
T1 | 194167 | 0 | 0 | 0 |
T3 | 0 | 60 | 0 | 0 |
T4 | 66811 | 0 | 0 | 0 |
T6 | 53729 | 0 | 0 | 0 |
T7 | 1622 | 1 | 0 | 0 |
T8 | 1430 | 0 | 0 | 0 |
T9 | 18975 | 4 | 0 | 0 |
T20 | 2327 | 9 | 0 | 0 |
T21 | 6506 | 0 | 0 | 0 |
T22 | 4360 | 3 | 0 | 0 |
T23 | 1362 | 0 | 0 | 0 |
T77 | 0 | 2 | 0 | 0 |
T82 | 0 | 6 | 0 | 0 |
T100 | 0 | 9 | 0 | 0 |
T109 | 0 | 7 | 0 | 0 |
T110 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 364425001 | 5268 | 0 | 0 |
T1 | 194167 | 0 | 0 | 0 |
T3 | 0 | 71 | 0 | 0 |
T4 | 66811 | 0 | 0 | 0 |
T6 | 53729 | 0 | 0 | 0 |
T7 | 1622 | 3 | 0 | 0 |
T8 | 1430 | 0 | 0 | 0 |
T9 | 18975 | 4 | 0 | 0 |
T20 | 2327 | 12 | 0 | 0 |
T21 | 6506 | 0 | 0 | 0 |
T22 | 4360 | 3 | 0 | 0 |
T23 | 1362 | 0 | 0 | 0 |
T77 | 0 | 2 | 0 | 0 |
T82 | 0 | 7 | 0 | 0 |
T100 | 0 | 10 | 0 | 0 |
T109 | 0 | 8 | 0 | 0 |
T110 | 0 | 9 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T9,T1 |
1 | 0 | Covered | T7,T9,T20 |
1 | 1 | Covered | T7,T9,T20 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 181346572 | 4325 | 0 | 0 |
g_div4.Div4Whole_A | 181346572 | 4938 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 181346572 | 4325 | 0 | 0 |
T1 | 97058 | 0 | 0 | 0 |
T3 | 0 | 58 | 0 | 0 |
T4 | 16310 | 0 | 0 | 0 |
T6 | 26811 | 0 | 0 | 0 |
T7 | 818 | 1 | 0 | 0 |
T8 | 669 | 0 | 0 | 0 |
T9 | 11186 | 4 | 0 | 0 |
T20 | 1290 | 9 | 0 | 0 |
T21 | 3186 | 0 | 0 | 0 |
T22 | 2284 | 3 | 0 | 0 |
T23 | 669 | 0 | 0 | 0 |
T77 | 0 | 2 | 0 | 0 |
T82 | 0 | 6 | 0 | 0 |
T100 | 0 | 9 | 0 | 0 |
T109 | 0 | 7 | 0 | 0 |
T110 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 181346572 | 4938 | 0 | 0 |
T1 | 97058 | 0 | 0 | 0 |
T3 | 0 | 63 | 0 | 0 |
T4 | 16310 | 0 | 0 | 0 |
T6 | 26811 | 0 | 0 | 0 |
T7 | 818 | 3 | 0 | 0 |
T8 | 669 | 0 | 0 | 0 |
T9 | 11186 | 4 | 0 | 0 |
T20 | 1290 | 8 | 0 | 0 |
T21 | 3186 | 0 | 0 | 0 |
T22 | 2284 | 3 | 0 | 0 |
T23 | 669 | 0 | 0 | 0 |
T77 | 0 | 2 | 0 | 0 |
T82 | 0 | 7 | 0 | 0 |
T100 | 0 | 10 | 0 | 0 |
T109 | 0 | 8 | 0 | 0 |
T110 | 0 | 9 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |