Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T9,T1
10CoveredT7,T9,T20
11CoveredT7,T9,T20

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 364425001 4425 0 0
g_div2.Div2Whole_A 364425001 5268 0 0
g_div4.Div4Stepped_A 181346572 4325 0 0
g_div4.Div4Whole_A 181346572 4938 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 364425001 4425 0 0
T1 194167 0 0 0
T3 0 60 0 0
T4 66811 0 0 0
T6 53729 0 0 0
T7 1622 1 0 0
T8 1430 0 0 0
T9 18975 4 0 0
T20 2327 9 0 0
T21 6506 0 0 0
T22 4360 3 0 0
T23 1362 0 0 0
T77 0 2 0 0
T82 0 6 0 0
T100 0 9 0 0
T109 0 7 0 0
T110 0 8 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 364425001 5268 0 0
T1 194167 0 0 0
T3 0 71 0 0
T4 66811 0 0 0
T6 53729 0 0 0
T7 1622 3 0 0
T8 1430 0 0 0
T9 18975 4 0 0
T20 2327 12 0 0
T21 6506 0 0 0
T22 4360 3 0 0
T23 1362 0 0 0
T77 0 2 0 0
T82 0 7 0 0
T100 0 10 0 0
T109 0 8 0 0
T110 0 9 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181346572 4325 0 0
T1 97058 0 0 0
T3 0 58 0 0
T4 16310 0 0 0
T6 26811 0 0 0
T7 818 1 0 0
T8 669 0 0 0
T9 11186 4 0 0
T20 1290 9 0 0
T21 3186 0 0 0
T22 2284 3 0 0
T23 669 0 0 0
T77 0 2 0 0
T82 0 6 0 0
T100 0 9 0 0
T109 0 7 0 0
T110 0 8 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181346572 4938 0 0
T1 97058 0 0 0
T3 0 63 0 0
T4 16310 0 0 0
T6 26811 0 0 0
T7 818 3 0 0
T8 669 0 0 0
T9 11186 4 0 0
T20 1290 8 0 0
T21 3186 0 0 0
T22 2284 3 0 0
T23 669 0 0 0
T77 0 2 0 0
T82 0 7 0 0
T100 0 10 0 0
T109 0 8 0 0
T110 0 9 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T9,T1
10CoveredT7,T9,T20
11CoveredT7,T9,T20

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 364425001 4425 0 0
g_div2.Div2Whole_A 364425001 5268 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 364425001 4425 0 0
T1 194167 0 0 0
T3 0 60 0 0
T4 66811 0 0 0
T6 53729 0 0 0
T7 1622 1 0 0
T8 1430 0 0 0
T9 18975 4 0 0
T20 2327 9 0 0
T21 6506 0 0 0
T22 4360 3 0 0
T23 1362 0 0 0
T77 0 2 0 0
T82 0 6 0 0
T100 0 9 0 0
T109 0 7 0 0
T110 0 8 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 364425001 5268 0 0
T1 194167 0 0 0
T3 0 71 0 0
T4 66811 0 0 0
T6 53729 0 0 0
T7 1622 3 0 0
T8 1430 0 0 0
T9 18975 4 0 0
T20 2327 12 0 0
T21 6506 0 0 0
T22 4360 3 0 0
T23 1362 0 0 0
T77 0 2 0 0
T82 0 7 0 0
T100 0 10 0 0
T109 0 8 0 0
T110 0 9 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T9,T1
10CoveredT7,T9,T20
11CoveredT7,T9,T20

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 181346572 4325 0 0
g_div4.Div4Whole_A 181346572 4938 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181346572 4325 0 0
T1 97058 0 0 0
T3 0 58 0 0
T4 16310 0 0 0
T6 26811 0 0 0
T7 818 1 0 0
T8 669 0 0 0
T9 11186 4 0 0
T20 1290 9 0 0
T21 3186 0 0 0
T22 2284 3 0 0
T23 669 0 0 0
T77 0 2 0 0
T82 0 6 0 0
T100 0 9 0 0
T109 0 7 0 0
T110 0 8 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181346572 4938 0 0
T1 97058 0 0 0
T3 0 63 0 0
T4 16310 0 0 0
T6 26811 0 0 0
T7 818 3 0 0
T8 669 0 0 0
T9 11186 4 0 0
T20 1290 8 0 0
T21 3186 0 0 0
T22 2284 3 0 0
T23 669 0 0 0
T77 0 2 0 0
T82 0 7 0 0
T100 0 10 0 0
T109 0 8 0 0
T110 0 9 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%