Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	453710505	406	0	0
StatusRise_A	453710505	406	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453710505	406	0	0
T2	52290	0	0	0
T4	208788	0	0	0
T5	134391	0	0	0
T23	3933	8	0	0
T24	433437	0	0	0
T25	5670	0	0	0
T37	6279	0	0	0
T38	0	6	0	0
T39	0	13	0	0
T46	0	17	0	0
T50	0	9	0	0
T82	5952	0	0	0
T100	6708	0	0	0
T109	5364	0	0	0
T148	0	9	0	0
T149	0	4	0	0
T181	0	11	0	0
T182	0	7	0	0
T183	0	14	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453710505	406	0	0
T2	52290	0	0	0
T4	208788	0	0	0
T5	134391	0	0	0
T23	3933	8	0	0
T24	433437	0	0	0
T25	5670	0	0	0
T37	6279	0	0	0
T38	0	6	0	0
T39	0	13	0	0
T46	0	17	0	0
T50	0	9	0	0
T82	5952	0	0	0
T100	6708	0	0	0
T109	5364	0	0	0
T148	0	9	0	0
T149	0	4	0	0
T181	0	11	0	0
T182	0	7	0	0
T183	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	151236835	134	0	0
StatusRise_A	151236835	134	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	134	0	0
T2	17430	0	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T23	1311	3	0	0
T24	144479	0	0	0
T25	1890	0	0	0
T37	2093	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	5	0	0
T50	0	3	0	0
T82	1984	0	0	0
T100	2236	0	0	0
T109	1788	0	0	0
T148	0	3	0	0
T149	0	2	0	0
T181	0	2	0	0
T182	0	3	0	0
T183	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	134	0	0
T2	17430	0	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T23	1311	3	0	0
T24	144479	0	0	0
T25	1890	0	0	0
T37	2093	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	5	0	0
T50	0	3	0	0
T82	1984	0	0	0
T100	2236	0	0	0
T109	1788	0	0	0
T148	0	3	0	0
T149	0	2	0	0
T181	0	2	0	0
T182	0	3	0	0
T183	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	151236835	136	0	0
StatusRise_A	151236835	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	136	0	0
T2	17430	0	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T23	1311	3	0	0
T24	144479	0	0	0
T25	1890	0	0	0
T37	2093	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1984	0	0	0
T100	2236	0	0	0
T109	1788	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0
T183	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	136	0	0
T2	17430	0	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T23	1311	3	0	0
T24	144479	0	0	0
T25	1890	0	0	0
T37	2093	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1984	0	0	0
T100	2236	0	0	0
T109	1788	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0
T183	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	151236835	136	0	0
StatusRise_A	151236835	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	136	0	0
T2	17430	0	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T23	1311	2	0	0
T24	144479	0	0	0
T25	1890	0	0	0
T37	2093	0	0	0
T38	0	2	0	0
T39	0	3	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1984	0	0	0
T100	2236	0	0	0
T109	1788	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151236835	136	0	0
T2	17430	0	0	0
T4	69596	0	0	0
T5	44797	0	0	0
T23	1311	2	0	0
T24	144479	0	0	0
T25	1890	0	0	0
T37	2093	0	0	0
T38	0	2	0	0
T39	0	3	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1984	0	0	0
T100	2236	0	0	0
T109	1788	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0