Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47470	0	0
CgEnOn_A	2147483647	38379	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47470	0	0
T1	436840	54	0	0
T2	1010616	0	0	0
T3	0	124	0	0
T4	683238	33	0	0
T5	908703	0	0	0
T6	120809	3	0	0
T7	3660	3	0	0
T8	3146	6	0	0
T9	45239	3	0	0
T20	5423	3	0	0
T21	41644	8	0	0
T22	28126	3	0	0
T23	15536	30	0	0
T24	1115350	0	0	0
T25	31936	6	0	0
T37	72336	9	0	0
T38	0	10	0	0
T39	0	25	0	0
T46	0	30	0	0
T50	0	15	0	0
T82	22649	0	0	0
T100	39163	0	0	0
T109	32154	0	0	0
T148	0	15	0	0
T149	0	5	0	0
T181	0	20	0	0
T182	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38379	0	0
T1	436840	51	0	0
T2	1010616	45	0	0
T3	0	553	0	0
T4	683238	0	0	0
T5	908703	0	0	0
T6	120809	0	0	0
T8	3146	3	0	0
T9	45239	0	0	0
T14	0	186	0	0
T20	5423	0	0	0
T21	41644	5	0	0
T22	28126	0	0	0
T23	15536	27	0	0
T24	1344104	0	0	0
T25	31936	6	0	0
T29	0	173	0	0
T37	72336	0	0	0
T38	0	10	0	0
T39	0	25	0	0
T46	0	30	0	0
T50	0	15	0	0
T75	0	30	0	0
T76	0	12	0	0
T82	22649	0	0	0
T100	39163	0	0	0
T109	32154	0	0	0
T148	0	15	0	0
T149	0	5	0	0
T165	0	39	0	0
T181	0	20	0	0
T182	0	10	0	0
T183	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	181346174	146	0	0
CgEnOn_A	181346174	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181346174	146	0	0
T2	104440	0	0	0
T3	0	1	0	0
T4	16309	0	0	0
T5	30188	0	0	0
T23	669	3	0	0
T24	46963	0	0	0
T25	1740	0	0	0
T37	4008	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	2558	0	0	0
T100	2349	0	0	0
T109	2007	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181346174	146	0	0
T2	104440	0	0	0
T3	0	1	0	0
T4	16309	0	0	0
T5	30188	0	0	0
T23	669	3	0	0
T24	46963	0	0	0
T25	1740	0	0	0
T37	4008	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	2558	0	0	0
T100	2349	0	0	0
T109	2007	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90672471	146	0	0
CgEnOn_A	90672471	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672471	146	0	0
T2	52220	0	0	0
T3	0	1	0	0
T4	8153	0	0	0
T5	15094	0	0	0
T23	334	3	0	0
T24	23481	0	0	0
T25	870	0	0	0
T37	2004	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1277	0	0	0
T100	1174	0	0	0
T109	1002	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672471	146	0	0
T2	52220	0	0	0
T3	0	1	0	0
T4	8153	0	0	0
T5	15094	0	0	0
T23	334	3	0	0
T24	23481	0	0	0
T25	870	0	0	0
T37	2004	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1277	0	0	0
T100	1174	0	0	0
T109	1002	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90672471	146	0	0
CgEnOn_A	90672471	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672471	146	0	0
T2	52220	0	0	0
T3	0	1	0	0
T4	8153	0	0	0
T5	15094	0	0	0
T23	334	3	0	0
T24	23481	0	0	0
T25	870	0	0	0
T37	2004	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1277	0	0	0
T100	1174	0	0	0
T109	1002	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672471	146	0	0
T2	52220	0	0	0
T3	0	1	0	0
T4	8153	0	0	0
T5	15094	0	0	0
T23	334	3	0	0
T24	23481	0	0	0
T25	870	0	0	0
T37	2004	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1277	0	0	0
T100	1174	0	0	0
T109	1002	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90672471	146	0	0
CgEnOn_A	90672471	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672471	146	0	0
T2	52220	0	0	0
T3	0	1	0	0
T4	8153	0	0	0
T5	15094	0	0	0
T23	334	3	0	0
T24	23481	0	0	0
T25	870	0	0	0
T37	2004	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1277	0	0	0
T100	1174	0	0	0
T109	1002	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672471	146	0	0
T2	52220	0	0	0
T3	0	1	0	0
T4	8153	0	0	0
T5	15094	0	0	0
T23	334	3	0	0
T24	23481	0	0	0
T25	870	0	0	0
T37	2004	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	1277	0	0	0
T100	1174	0	0	0
T109	1002	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	364424552	146	0	0
CgEnOn_A	364424552	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364424552	146	0	0
T2	209162	0	0	0
T3	0	1	0	0
T4	66810	0	0	0
T5	107511	0	0	0
T23	1362	3	0	0
T24	94019	0	0	0
T25	3559	0	0	0
T37	8040	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	4537	0	0	0
T100	4295	0	0	0
T109	3502	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364424552	139	0	0
T2	209162	0	0	0
T4	66810	0	0	0
T5	107511	0	0	0
T23	1362	3	0	0
T24	94019	0	0	0
T25	3559	0	0	0
T37	8040	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	4537	0	0	0
T100	4295	0	0	0
T109	3502	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	4	0	0
T182	0	2	0	0
T183	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	388844616	135	0	0
CgEnOn_A	388844616	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	135	0	0
T2	217884	0	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	0	0	0
T37	8376	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	5	0	0
T50	0	3	0	0
T82	4727	0	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T148	0	3	0	0
T149	0	2	0	0
T181	0	2	0	0
T182	0	3	0	0
T183	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	134	0	0
T2	217884	0	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	0	0	0
T37	8376	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	5	0	0
T50	0	3	0	0
T82	4727	0	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T148	0	3	0	0
T149	0	2	0	0
T181	0	2	0	0
T182	0	3	0	0
T183	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	388844616	135	0	0
CgEnOn_A	388844616	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	135	0	0
T2	217884	0	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	0	0	0
T37	8376	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	5	0	0
T50	0	3	0	0
T82	4727	0	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T148	0	3	0	0
T149	0	2	0	0
T181	0	2	0	0
T182	0	3	0	0
T183	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	134	0	0
T2	217884	0	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	0	0	0
T37	8376	0	0	0
T38	0	2	0	0
T39	0	5	0	0
T46	0	5	0	0
T50	0	3	0	0
T82	4727	0	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T148	0	3	0	0
T149	0	2	0	0
T181	0	2	0	0
T182	0	3	0	0
T183	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	186689589	137	0	0
CgEnOn_A	186689589	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186689589	137	0	0
T2	104586	0	0	0
T4	33406	0	0	0
T5	53758	0	0	0
T23	692	2	0	0
T24	64291	0	0	0
T25	1779	0	0	0
T37	4020	0	0	0
T38	0	2	0	0
T39	0	3	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	2269	0	0	0
T100	2147	0	0	0
T109	1751	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186689589	136	0	0
T2	104586	0	0	0
T4	33406	0	0	0
T5	53758	0	0	0
T23	692	2	0	0
T24	64291	0	0	0
T25	1779	0	0	0
T37	4020	0	0	0
T38	0	2	0	0
T39	0	3	0	0
T46	0	6	0	0
T50	0	3	0	0
T82	2269	0	0	0
T100	2147	0	0	0
T109	1751	0	0	0
T148	0	3	0	0
T149	0	1	0	0
T181	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T38,T39
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90672471	7493	0	0
CgEnOn_A	90672471	5228	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672471	7493	0	0
T1	48529	19	0	0
T4	8153	11	0	0
T6	13405	1	0	0
T7	409	1	0	0
T8	334	2	0	0
T9	5592	1	0	0
T20	644	1	0	0
T21	1593	1	0	0
T22	1141	1	0	0
T23	334	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90672471	5228	0	0
T1	48529	18	0	0
T2	0	16	0	0
T3	0	142	0	0
T4	8153	0	0	0
T6	13405	0	0	0
T8	334	1	0	0
T9	5592	0	0	0
T14	0	60	0	0
T20	644	0	0	0
T21	1593	0	0	0
T22	1141	0	0	0
T23	334	3	0	0
T24	23481	0	0	0
T29	0	54	0	0
T75	0	9	0	0
T76	0	4	0	0
T165	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T38,T39
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	181346174	7574	0	0
CgEnOn_A	181346174	5309	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181346174	7574	0	0
T1	97057	17	0	0
T4	16309	11	0	0
T6	26811	1	0	0
T7	818	1	0	0
T8	668	2	0	0
T9	11185	1	0	0
T20	1289	1	0	0
T21	3185	1	0	0
T22	2283	1	0	0
T23	669	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181346174	5309	0	0
T1	97057	16	0	0
T2	0	13	0	0
T3	0	140	0	0
T4	16309	0	0	0
T6	26811	0	0	0
T8	668	1	0	0
T9	11185	0	0	0
T14	0	63	0	0
T20	1289	0	0	0
T21	3185	0	0	0
T22	2283	0	0	0
T23	669	3	0	0
T24	46963	0	0	0
T29	0	47	0	0
T75	0	10	0	0
T76	0	4	0	0
T165	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T38,T39
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	364424552	7556	0	0
CgEnOn_A	364424552	5284	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364424552	7556	0	0
T1	194166	18	0	0
T4	66810	11	0	0
T6	53728	1	0	0
T7	1622	1	0	0
T8	1429	2	0	0
T9	18975	1	0	0
T20	2327	1	0	0
T21	6505	1	0	0
T22	4359	1	0	0
T23	1362	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364424552	5284	0	0
T1	194166	17	0	0
T2	0	14	0	0
T3	0	148	0	0
T4	66810	0	0	0
T6	53728	0	0	0
T8	1429	1	0	0
T9	18975	0	0	0
T14	0	63	0	0
T20	2327	0	0	0
T21	6505	0	0	0
T22	4359	0	0	0
T23	1362	3	0	0
T24	94019	0	0	0
T29	0	50	0	0
T75	0	11	0	0
T76	0	4	0	0
T165	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T38,T39
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	186689589	7543	0	0
CgEnOn_A	186689589	5268	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186689589	7543	0	0
T1	97088	17	0	0
T4	33406	11	0	0
T6	26865	1	0	0
T7	811	1	0	0
T8	715	2	0	0
T9	9487	1	0	0
T20	1163	1	0	0
T21	3253	1	0	0
T22	2179	1	0	0
T23	692	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186689589	5268	0	0
T1	97088	16	0	0
T2	0	14	0	0
T3	0	138	0	0
T4	33406	0	0	0
T6	26865	0	0	0
T8	715	1	0	0
T9	9487	0	0	0
T14	0	59	0	0
T20	1163	0	0	0
T21	3253	0	0	0
T22	2179	0	0	0
T23	692	2	0	0
T24	64291	0	0	0
T29	0	52	0	0
T75	0	12	0	0
T76	0	4	0	0
T165	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Covered	T21,T25,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	388844616	4049	0	0
CgEnOn_A	388844616	4048	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	4049	0	0
T2	0	2	0	0
T3	0	119	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T21	6777	5	0	0
T22	4541	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	6	0	0
T29	0	22	0	0
T37	8376	9	0	0
T78	0	8	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T112	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	4048	0	0
T2	0	2	0	0
T3	0	119	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T21	6777	5	0	0
T22	4541	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	6	0	0
T29	0	22	0	0
T37	8376	9	0	0
T78	0	8	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T112	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Covered	T21,T25,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	388844616	4059	0	0
CgEnOn_A	388844616	4058	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	4059	0	0
T2	0	3	0	0
T3	0	115	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T21	6777	5	0	0
T22	4541	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	3	0	0
T29	0	22	0	0
T37	8376	5	0	0
T78	0	11	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T111	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	4058	0	0
T2	0	3	0	0
T3	0	115	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T21	6777	5	0	0
T22	4541	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	3	0	0
T29	0	22	0	0
T37	8376	5	0	0
T78	0	11	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Covered	T21,T25,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	388844616	4016	0	0
CgEnOn_A	388844616	4015	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	4016	0	0
T2	0	4	0	0
T3	0	107	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T21	6777	4	0	0
T22	4541	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	5	0	0
T29	0	15	0	0
T37	8376	5	0	0
T78	0	8	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T111	0	1	0	0
T112	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	4015	0	0
T2	0	4	0	0
T3	0	107	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T21	6777	4	0	0
T22	4541	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	5	0	0
T29	0	15	0	0
T37	8376	5	0	0
T78	0	8	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T111	0	1	0	0
T112	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T4,T5
1	0	Covered	T21,T25,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	388844616	4043	0	0
CgEnOn_A	388844616	4042	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	4043	0	0
T2	0	2	0	0
T3	0	115	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T21	6777	7	0	0
T22	4541	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	5	0	0
T29	0	24	0	0
T37	8376	8	0	0
T78	0	10	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T112	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388844616	4042	0	0
T2	0	2	0	0
T3	0	115	0	0
T4	69596	0	0	0
T5	111994	0	0	0
T21	6777	7	0	0
T22	4541	0	0	0
T23	1459	3	0	0
T24	139939	0	0	0
T25	3708	5	0	0
T29	0	24	0	0
T37	8376	8	0	0
T78	0	10	0	0
T80	0	1	0	0
T100	4475	0	0	0
T109	3648	0	0	0
T112	0	7	0	0