Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	581067	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3218541

1

T6

28

T7

14

T4

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	938963	1			T6	42		T7	13		T4	48
values[0x0]	1316230	1			T6	19		T7	14		T4	25
values[0x1]	1544415	1			T6	20		T7	13		T4	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	326595	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3473013

1

T6

34

T7

17

T4

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14203	1			T28	9		T20	1		T11	3
valid_sources[0x01]	14770	1			T4	1		T29	1		T20	1
valid_sources[0x02]	14424	1			T7	1		T4	4		T5	7
valid_sources[0x03]	15230	1			T6	81		T4	1		T2	4
valid_sources[0x04]	15298	1			T20	1		T22	1		T3	1
valid_sources[0x05]	14241	1			T29	1		T2	126		T22	1
valid_sources[0x06]	15732	1			T2	535		T11	5		T31	4
valid_sources[0x07]	14699	1			T5	48		T2	1		T23	2
valid_sources[0x08]	15248	1			T20	1		T2	14		T3	2
valid_sources[0x09]	13134	1			T4	1		T11	3		T31	2
valid_sources[0x0a]	14661	1			T4	1		T2	12		T11	3
valid_sources[0x0b]	15336	1			T20	10		T2	2		T24	1
valid_sources[0x0c]	15077	1			T29	1		T20	1		T2	322
valid_sources[0x0d]	14930	1			T4	1		T2	526		T24	1
valid_sources[0x0e]	13285	1			T2	60		T11	26		T31	1
valid_sources[0x0f]	14322	1			T11	2		T31	2		T34	1
valid_sources[0x10]	14312	1			T4	1		T29	1		T2	4
valid_sources[0x11]	15464	1			T20	2		T2	299		T3	2
valid_sources[0x12]	14393	1			T4	3		T26	1		T20	1
valid_sources[0x13]	14984	1			T2	442		T3	1		T11	5
valid_sources[0x14]	13864	1			T22	1		T3	1		T11	10
valid_sources[0x15]	13783	1			T4	1		T5	6		T18	1
valid_sources[0x16]	14813	1			T29	2		T2	152		T3	1
valid_sources[0x17]	14601	1			T26	1		T24	1		T11	4
valid_sources[0x18]	15455	1			T29	4		T2	186		T11	4
valid_sources[0x19]	15139	1			T26	1		T22	2		T24	1
valid_sources[0x1a]	13880	1			T18	2		T2	2		T22	1
valid_sources[0x1b]	15636	1			T26	1		T2	39		T3	1
valid_sources[0x1c]	15787	1			T18	1		T2	191		T3	1
valid_sources[0x1d]	14143	1			T11	20		T31	3		T32	19
valid_sources[0x1e]	14023	1			T29	1		T22	2		T3	1
valid_sources[0x1f]	14369	1			T7	9		T2	226		T22	1
valid_sources[0x20]	13944	1			T7	5		T29	1		T11	4
valid_sources[0x21]	13661	1			T29	2		T18	4		T2	134
valid_sources[0x22]	14635	1			T2	170		T24	5		T11	11
valid_sources[0x23]	15294	1			T28	8		T5	6		T2	4
valid_sources[0x24]	16349	1			T2	478		T24	1		T11	3
valid_sources[0x25]	15236	1			T2	43		T24	1		T32	23
valid_sources[0x26]	15038	1			T28	5		T2	1		T11	6
valid_sources[0x27]	15839	1			T28	1		T20	4		T2	489
valid_sources[0x28]	13614	1			T5	35		T2	2		T3	1
valid_sources[0x29]	15990	1			T2	96		T24	1		T11	24
valid_sources[0x2a]	15860	1			T5	59		T2	463		T11	4
valid_sources[0x2b]	15268	1			T2	96		T11	2		T32	5
valid_sources[0x2c]	15254	1			T22	2		T3	1		T24	1
valid_sources[0x2d]	13258	1			T20	1		T2	19		T22	1
valid_sources[0x2e]	14725	1			T7	6		T2	8		T11	4
valid_sources[0x2f]	15618	1			T22	1		T3	4		T24	1
valid_sources[0x30]	14981	1			T2	270		T22	1		T12	111
valid_sources[0x31]	15199	1			T7	1		T2	11		T11	3
valid_sources[0x32]	13435	1			T29	2		T2	40		T22	1
valid_sources[0x33]	14593	1			T4	1		T20	2		T11	8
valid_sources[0x34]	14765	1			T11	16		T31	3		T12	129
valid_sources[0x35]	14592	1			T26	1		T11	7		T31	2
valid_sources[0x36]	14161	1			T4	2		T22	2		T23	1
valid_sources[0x37]	15536	1			T28	8		T29	1		T24	1
valid_sources[0x38]	14579	1			T2	212		T11	15		T31	1
valid_sources[0x39]	14135	1			T3	1		T11	3		T31	5
valid_sources[0x3a]	14952	1			T24	1		T31	3		T32	11
valid_sources[0x3b]	15384	1			T29	3		T2	97		T24	1
valid_sources[0x3c]	14653	1			T4	1		T2	38		T22	1
valid_sources[0x3d]	14993	1			T2	1		T3	6		T24	1
valid_sources[0x3e]	14170	1			T2	5		T11	3		T31	2
valid_sources[0x3f]	16841	1			T20	3		T3	1		T24	2
valid_sources[0x40]	15507	1			T29	2		T20	1		T2	405
valid_sources[0x41]	13794	1			T4	3		T18	1		T2	203
valid_sources[0x42]	15873	1			T18	10		T2	29		T24	1
valid_sources[0x43]	15805	1			T20	3		T2	143		T22	2
valid_sources[0x44]	14688	1			T29	1		T2	126		T11	2
valid_sources[0x45]	14483	1			T7	1		T2	190		T11	1
valid_sources[0x46]	14387	1			T26	1		T29	3		T2	408
valid_sources[0x47]	16475	1			T11	6		T31	1		T151	3
valid_sources[0x48]	15867	1			T4	1		T29	1		T2	96
valid_sources[0x49]	16006	1			T2	7		T22	1		T11	12
valid_sources[0x4a]	13707	1			T2	11		T24	1		T11	2
valid_sources[0x4b]	16492	1			T7	5		T5	18		T2	82
valid_sources[0x4c]	14022	1			T7	2		T5	4		T2	137
valid_sources[0x4d]	14972	1			T5	1		T18	3		T3	1
valid_sources[0x4e]	16255	1			T4	1		T2	329		T3	3
valid_sources[0x4f]	13385	1			T2	148		T24	1		T11	6
valid_sources[0x50]	14404	1			T4	1		T2	64		T22	1
valid_sources[0x51]	13748	1			T4	1		T2	11		T11	1
valid_sources[0x52]	14823	1			T5	17		T2	52		T3	1
valid_sources[0x53]	13627	1			T5	5		T2	143		T31	2
valid_sources[0x54]	14144	1			T3	2		T24	1		T11	2
valid_sources[0x55]	14752	1			T3	3		T11	8		T34	1
valid_sources[0x56]	18813	1			T18	3		T2	8		T3	2
valid_sources[0x57]	13735	1			T29	5		T2	502		T3	1
valid_sources[0x58]	13043	1			T29	3		T2	10		T22	1
valid_sources[0x59]	16134	1			T18	4		T21	105		T2	144
valid_sources[0x5a]	15138	1			T18	16		T2	1		T11	1
valid_sources[0x5b]	15105	1			T28	4		T29	1		T2	196
valid_sources[0x5c]	15020	1			T26	1		T5	1		T2	129
valid_sources[0x5d]	15330	1			T29	4		T22	1		T11	20
valid_sources[0x5e]	14620	1			T4	2		T11	9		T31	1
valid_sources[0x5f]	15668	1			T28	9		T2	197		T24	1
valid_sources[0x60]	15003	1			T18	3		T2	2		T3	3
valid_sources[0x61]	14115	1			T4	5		T2	102		T3	2
valid_sources[0x62]	14768	1			T18	2		T2	316		T3	3
valid_sources[0x63]	17700	1			T4	1		T2	616		T24	1
valid_sources[0x64]	15968	1			T29	1		T11	2		T151	1
valid_sources[0x65]	14180	1			T4	5		T26	1		T22	1
valid_sources[0x66]	15206	1			T4	1		T2	114		T22	1
valid_sources[0x67]	14089	1			T4	1		T20	5		T2	5
valid_sources[0x68]	14917	1			T28	1		T29	3		T2	185
valid_sources[0x69]	14477	1			T2	105		T3	1		T11	9
valid_sources[0x6a]	15666	1			T26	1		T2	310		T11	4
valid_sources[0x6b]	14042	1			T28	2		T2	287		T11	1
valid_sources[0x6c]	14224	1			T2	84		T3	2		T24	1
valid_sources[0x6d]	15055	1			T29	1		T2	4		T11	9
valid_sources[0x6e]	14173	1			T29	2		T2	1		T11	2
valid_sources[0x6f]	15796	1			T5	15		T18	1		T2	142
valid_sources[0x70]	14525	1			T4	1		T2	1		T22	1
valid_sources[0x71]	15684	1			T2	165		T24	1		T11	12
valid_sources[0x72]	14596	1			T28	5		T20	2		T2	6
valid_sources[0x73]	14321	1			T4	1		T24	1		T11	11
valid_sources[0x74]	14774	1			T2	118		T11	24		T32	21
valid_sources[0x75]	16943	1			T1	1711		T2	88		T11	11
valid_sources[0x76]	15573	1			T25	27		T29	1		T18	1
valid_sources[0x77]	17285	1			T23	4		T24	1		T11	1
valid_sources[0x78]	14089	1			T4	1		T26	1		T28	2
valid_sources[0x79]	14552	1			T26	1		T28	5		T2	256
valid_sources[0x7a]	15021	1			T20	1		T2	8		T22	1
valid_sources[0x7b]	13544	1			T29	1		T18	12		T2	70
valid_sources[0x7c]	15320	1			T2	6		T22	1		T3	3
valid_sources[0x7d]	15537	1			T5	6		T2	38		T24	2
valid_sources[0x7e]	16671	1			T4	1		T29	1		T5	2
valid_sources[0x7f]	15525	1			T20	1		T2	186		T3	1
valid_sources[0x80]	14569	1			T4	1		T29	1		T19	112

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

814965

1

T6

21

T7

4

T4

29

values[0x0]

all_enables

biggest_size

1224607

1

T6

5

T7

6

T4

11

values[0x1]

all_enables

biggest_size

1178969

1

T6

2

T7

4

T4

8