Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T25
0	1	Covered	T25,T1,T2
1	0	Covered	T6,T7,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T25
1	0	Covered	T27,T41,T42
1	1	Covered	T6,T7,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1310505954	14289	0	0
GateOpen_A	1310505954	20943	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1310505954	14289	0	0
T1	1209815	60	0	0
T2	0	117	0	0
T4	32486	0	0	0
T5	106830	0	0	0
T6	7830	4	0	0
T7	15176	0	0	0
T11	0	26	0	0
T23	0	15	0	0
T25	5040	33	0	0
T26	9723	0	0	0
T27	3660	20	0	0
T28	3564	3	0	0
T29	37205	0	0	0
T41	0	1	0	0
T70	0	4	0	0
T147	0	36	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1310505954	20943	0	0
T1	1209815	84	0	0
T2	0	125	0	0
T4	32486	12	0	0
T5	106830	32	0	0
T6	7830	8	0	0
T7	15176	0	0	0
T21	0	4	0	0
T23	0	19	0	0
T25	5040	37	0	0
T26	9723	0	0	0
T27	3660	24	0	0
T28	3564	7	0	0
T29	37205	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T25
0	1	Covered	T25,T1,T2
1	0	Covered	T6,T7,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T25
1	0	Covered	T27,T41,T42
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	144798988	3417	0	0
GateOpen_A	144798988	5079	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798988	3417	0	0
T1	134516	15	0	0
T2	0	26	0	0
T4	2799	0	0	0
T5	7385	0	0	0
T6	855	1	0	0
T7	1761	0	0	0
T11	0	5	0	0
T23	0	4	0	0
T25	545	9	0	0
T26	1098	0	0	0
T27	406	5	0	0
T28	374	0	0	0
T29	4123	0	0	0
T41	0	1	0	0
T70	0	1	0	0
T147	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798988	5079	0	0
T1	134516	21	0	0
T2	0	28	0	0
T4	2799	3	0	0
T5	7385	8	0	0
T6	855	2	0	0
T7	1761	0	0	0
T21	0	1	0	0
T23	0	5	0	0
T25	545	10	0	0
T26	1098	0	0	0
T27	406	6	0	0
T28	374	1	0	0
T29	4123	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T25
0	1	Covered	T25,T1,T2
1	0	Covered	T6,T7,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T25
1	0	Covered	T27,T41,T42
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	289598645	3616	0	0
GateOpen_A	289598645	5278	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289598645	3616	0	0
T1	269036	16	0	0
T2	0	30	0	0
T4	5597	0	0	0
T5	14771	0	0	0
T6	1709	1	0	0
T7	3521	0	0	0
T11	0	7	0	0
T23	0	3	0	0
T25	1089	8	0	0
T26	2196	0	0	0
T27	811	5	0	0
T28	748	1	0	0
T29	8246	0	0	0
T70	0	1	0	0
T147	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289598645	5278	0	0
T1	269036	22	0	0
T2	0	32	0	0
T4	5597	3	0	0
T5	14771	8	0	0
T6	1709	2	0	0
T7	3521	0	0	0
T21	0	1	0	0
T23	0	4	0	0
T25	1089	9	0	0
T26	2196	0	0	0
T27	811	6	0	0
T28	748	2	0	0
T29	8246	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T25
0	1	Covered	T25,T1,T2
1	0	Covered	T6,T7,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T25
1	0	Covered	T27,T41,T42
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	580558750	3617	0	0
GateOpen_A	580558750	5282	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580558750	3617	0	0
T1	537500	15	0	0
T2	0	31	0	0
T4	16060	0	0	0
T5	56448	0	0	0
T6	3511	1	0	0
T7	6596	0	0	0
T11	0	7	0	0
T23	0	4	0	0
T25	2271	6	0	0
T26	4286	0	0	0
T27	1660	5	0	0
T28	1628	1	0	0
T29	16557	0	0	0
T70	0	1	0	0
T147	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580558750	5282	0	0
T1	537500	21	0	0
T2	0	33	0	0
T4	16060	3	0	0
T5	56448	8	0	0
T6	3511	2	0	0
T7	6596	0	0	0
T21	0	1	0	0
T23	0	5	0	0
T25	2271	7	0	0
T26	4286	0	0	0
T27	1660	6	0	0
T28	1628	2	0	0
T29	16557	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T25
0	1	Covered	T25,T1,T2
1	0	Covered	T6,T7,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T25
1	0	Covered	T27,T41,T42
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	295549571	3639	0	0
GateOpen_A	295549571	5304	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295549571	3639	0	0
T1	268763	14	0	0
T2	0	30	0	0
T4	8030	0	0	0
T5	28226	0	0	0
T6	1755	1	0	0
T7	3298	0	0	0
T11	0	7	0	0
T23	0	4	0	0
T25	1135	10	0	0
T26	2143	0	0	0
T27	783	5	0	0
T28	814	1	0	0
T29	8279	0	0	0
T70	0	1	0	0
T147	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295549571	5304	0	0
T1	268763	20	0	0
T2	0	32	0	0
T4	8030	3	0	0
T5	28226	8	0	0
T6	1755	2	0	0
T7	3298	0	0	0
T21	0	1	0	0
T23	0	5	0	0
T25	1135	11	0	0
T26	2143	0	0	0
T27	783	6	0	0
T28	814	2	0	0
T29	8279	0	0	0