Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	740113450	65297	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740113450	65297	0	0
T1	1343815	535	0	0
T2	671360	91	0	0
T3	127940	50	0	0
T11	0	109	0	0
T12	0	330	0	0
T13	0	131	0	0
T14	0	469	0	0
T15	0	77	0	0
T16	0	223	0	0
T17	0	1265	0	0
T18	18405	0	0	0
T19	13515	0	0	0
T20	79095	0	0	0
T21	11765	0	0	0
T22	11470	0	0	0
T23	6925	0	0	0
T24	234625	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148022690	9861	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	9861	0	0
T1	268763	77	0	0
T2	134272	12	0	0
T3	25588	8	0	0
T11	0	16	0	0
T12	0	47	0	0
T13	0	19	0	0
T14	0	76	0	0
T15	0	15	0	0
T16	0	43	0	0
T17	0	187	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T22	2294	0	0	0
T23	1385	0	0	0
T24	46925	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148022690	9616	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	9616	0	0
T1	268763	76	0	0
T2	134272	13	0	0
T3	25588	8	0	0
T11	0	14	0	0
T12	0	46	0	0
T13	0	19	0	0
T14	0	74	0	0
T15	0	15	0	0
T16	0	43	0	0
T17	0	156	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T22	2294	0	0	0
T23	1385	0	0	0
T24	46925	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148022690	13064	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	13064	0	0
T1	268763	120	0	0
T2	134272	18	0	0
T3	25588	10	0	0
T11	0	21	0	0
T12	0	66	0	0
T13	0	26	0	0
T14	0	95	0	0
T15	0	15	0	0
T16	0	43	0	0
T17	0	247	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T22	2294	0	0	0
T23	1385	0	0	0
T24	46925	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148022690	13089	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	13089	0	0
T1	268763	104	0	0
T2	134272	18	0	0
T3	25588	10	0	0
T11	0	21	0	0
T12	0	66	0	0
T13	0	26	0	0
T14	0	96	0	0
T15	0	15	0	0
T16	0	43	0	0
T17	0	256	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T22	2294	0	0	0
T23	1385	0	0	0
T24	46925	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	148022690	19667	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	19667	0	0
T1	268763	158	0	0
T2	134272	30	0	0
T3	25588	14	0	0
T11	0	37	0	0
T12	0	105	0	0
T13	0	41	0	0
T14	0	128	0	0
T15	0	17	0	0
T16	0	51	0	0
T17	0	419	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T22	2294	0	0	0
T23	1385	0	0	0
T24	46925	0	0	0