Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	148022690	145587839	0	0
AllClkBypReqTrue_A	148022690	126126	0	0
IoClkBypReqFalse_A	148022690	145510276	0	2415
IoClkBypReqTrue_A	148022690	199023	0	0
LcClkBypAckFalse_A	148022690	145597940	0	0
LcClkBypAckTrue_A	148022690	116025	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	145587839	0	0
T1	268763	267835	0	0
T4	4014	846	0	0
T5	56447	4513	0	0
T6	1827	1735	0	0
T7	1167	1078	0	0
T25	1560	1448	0	0
T26	1115	1061	0	0
T27	1811	1689	0	0
T28	1680	1398	0	0
T29	2931	2911	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	126126	0	0
T1	268763	419	0	0
T2	0	1202	0	0
T4	4014	0	0	0
T5	56447	0	0	0
T7	1167	65	0	0
T11	0	433	0	0
T12	0	1322	0	0
T13	0	283	0	0
T18	3681	0	0	0
T22	0	273	0	0
T25	1560	0	0	0
T26	1115	11	0	0
T27	1811	0	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T111	0	17	0	0
T112	0	262	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	145510276	0	2415
T1	268763	267612	0	3
T4	4014	840	0	3
T5	56447	4495	0	3
T6	1827	1733	0	3
T7	1167	1121	0	3
T25	1560	1446	0	3
T26	1115	885	0	3
T27	1811	1687	0	3
T28	1680	1396	0	3
T29	2931	2909	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	199023	0	0
T1	268763	630	0	0
T2	0	1704	0	0
T4	4014	0	0	0
T5	56447	0	0	0
T7	1167	20	0	0
T11	0	722	0	0
T12	0	2139	0	0
T13	0	318	0	0
T18	3681	0	0	0
T22	0	41	0	0
T25	1560	0	0	0
T26	1115	185	0	0
T27	1811	0	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T111	0	250	0	0
T113	0	24	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	145597940	0	0
T1	268763	267829	0	0
T4	4014	846	0	0
T5	56447	4513	0	0
T6	1827	1735	0	0
T7	1167	1128	0	0
T25	1560	1448	0	0
T26	1115	1025	0	0
T27	1811	1689	0	0
T28	1680	1398	0	0
T29	2931	2911	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	116025	0	0
T1	268763	425	0	0
T2	0	904	0	0
T4	4014	0	0	0
T5	56447	0	0	0
T7	1167	15	0	0
T11	0	483	0	0
T12	0	1393	0	0
T13	0	188	0	0
T18	3681	0	0	0
T22	0	37	0	0
T25	1560	0	0	0
T26	1115	47	0	0
T27	1811	0	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T111	0	95	0	0
T113	0	19	0	0