Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16993	0	0
TransStop_A	2147483647	8844	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16993	0	0
T1	2239656	101	0	0
T2	0	136	0	0
T4	66916	0	0	0
T5	235208	0	0	0
T6	14628	4	0	0
T7	27484	0	0	0
T11	0	82	0	0
T18	0	32	0	0
T19	0	30	0	0
T21	0	27	0	0
T25	9460	0	0	0
T26	17860	0	0	0
T27	6492	0	0	0
T28	6784	4	0	0
T29	68988	33	0	0
T70	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8844	0	0
T1	2239656	60	0	0
T2	0	61	0	0
T4	66916	0	0	0
T5	235208	0	0	0
T6	14628	4	0	0
T7	27484	0	0	0
T11	0	51	0	0
T18	0	21	0	0
T19	0	13	0	0
T21	0	19	0	0
T25	9460	0	0	0
T26	17860	0	0	0
T27	6492	0	0	0
T28	6784	4	0	0
T29	68988	21	0	0
T70	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	615557307	4243	0	0
TransStop_A	615557307	2202	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615557307	4243	0	0
T1	559914	29	0	0
T2	0	43	0	0
T4	16729	0	0	0
T5	58802	0	0	0
T6	3657	1	0	0
T7	6871	0	0	0
T11	0	21	0	0
T18	0	6	0	0
T19	0	6	0	0
T21	0	5	0	0
T25	2365	0	0	0
T26	4465	0	0	0
T27	1623	0	0	0
T28	1696	1	0	0
T29	17247	9	0	0
T70	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615557307	2202	0	0
T1	559914	18	0	0
T2	0	20	0	0
T4	16729	0	0	0
T5	58802	0	0	0
T6	3657	1	0	0
T7	6871	0	0	0
T11	0	11	0	0
T18	0	4	0	0
T19	0	4	0	0
T21	0	4	0	0
T25	2365	0	0	0
T26	4465	0	0	0
T27	1623	0	0	0
T28	1696	1	0	0
T29	17247	4	0	0
T70	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	615557307	4255	0	0
TransStop_A	615557307	2208	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615557307	4255	0	0
T1	559914	21	0	0
T2	0	38	0	0
T4	16729	0	0	0
T5	58802	0	0	0
T6	3657	1	0	0
T7	6871	0	0	0
T11	0	18	0	0
T18	0	10	0	0
T19	0	7	0	0
T21	0	6	0	0
T25	2365	0	0	0
T26	4465	0	0	0
T27	1623	0	0	0
T28	1696	1	0	0
T29	17247	7	0	0
T70	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615557307	2208	0	0
T1	559914	11	0	0
T2	0	17	0	0
T4	16729	0	0	0
T5	58802	0	0	0
T6	3657	1	0	0
T7	6871	0	0	0
T11	0	11	0	0
T18	0	6	0	0
T19	0	2	0	0
T21	0	5	0	0
T25	2365	0	0	0
T26	4465	0	0	0
T27	1623	0	0	0
T28	1696	1	0	0
T29	17247	4	0	0
T70	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	615557307	4252	0	0
TransStop_A	615557307	2244	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615557307	4252	0	0
T1	559914	26	0	0
T2	0	27	0	0
T4	16729	0	0	0
T5	58802	0	0	0
T6	3657	1	0	0
T7	6871	0	0	0
T11	0	19	0	0
T18	0	9	0	0
T19	0	9	0	0
T21	0	8	0	0
T25	2365	0	0	0
T26	4465	0	0	0
T27	1623	0	0	0
T28	1696	1	0	0
T29	17247	10	0	0
T70	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615557307	2244	0	0
T1	559914	15	0	0
T2	0	13	0	0
T4	16729	0	0	0
T5	58802	0	0	0
T6	3657	1	0	0
T7	6871	0	0	0
T11	0	12	0	0
T18	0	5	0	0
T19	0	5	0	0
T21	0	5	0	0
T25	2365	0	0	0
T26	4465	0	0	0
T27	1623	0	0	0
T28	1696	1	0	0
T29	17247	7	0	0
T70	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	615557307	4243	0	0
TransStop_A	615557307	2190	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615557307	4243	0	0
T1	559914	25	0	0
T2	0	28	0	0
T4	16729	0	0	0
T5	58802	0	0	0
T6	3657	1	0	0
T7	6871	0	0	0
T11	0	24	0	0
T18	0	7	0	0
T19	0	8	0	0
T21	0	8	0	0
T25	2365	0	0	0
T26	4465	0	0	0
T27	1623	0	0	0
T28	1696	1	0	0
T29	17247	7	0	0
T70	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615557307	2190	0	0
T1	559914	16	0	0
T2	0	11	0	0
T4	16729	0	0	0
T5	58802	0	0	0
T6	3657	1	0	0
T7	6871	0	0	0
T11	0	17	0	0
T18	0	6	0	0
T19	0	2	0	0
T21	0	5	0	0
T25	2365	0	0	0
T26	4465	0	0	0
T27	1623	0	0	0
T28	1696	1	0	0
T29	17247	6	0	0
T70	0	1	0	0