Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T7,T4
01CoveredT6,T7,T4
10CoveredT7,T26,T1 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T7,T4
10CoveredT7,T26,T1
11CoveredT7,T26,T1 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT7,T26,T1
10CoveredT6,T7,T4
11CoveredT6,T7,T4
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 723652057 723649642 0 0
selKnown1 1741674897 1741672482 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 723652057 723649642 0 0
T1 672036 672033 0 0
T4 13990 13987 0 0
T5 36926 36923 0 0
T6 4270 4267 0 0
T7 8524 8521 0 0
T25 2722 2719 0 0
T26 5368 5365 0 0
T27 2027 2024 0 0
T28 1868 1865 0 0
T29 20613 20610 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1741674897 1741672482 0 0
T1 1612500 1612497 0 0
T4 48177 48174 0 0
T5 169341 169338 0 0
T6 10530 10527 0 0
T7 19788 19785 0 0
T25 6810 6807 0 0
T26 12855 12852 0 0
T27 4977 4974 0 0
T28 4884 4881 0 0
T29 49668 49665 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T7,T4
01CoveredT6,T7,T4
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T7,T4
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T7,T4
11CoveredT6,T7,T4
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 289598255 289597450 0 0
selKnown1 580558299 580557494 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 289598255 289597450 0 0
T1 269035 269034 0 0
T4 5596 5595 0 0
T5 14771 14770 0 0
T6 1708 1707 0 0
T7 3520 3519 0 0
T25 1089 1088 0 0
T26 2195 2194 0 0
T27 811 810 0 0
T28 747 746 0 0
T29 8245 8244 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 580558299 580557494 0 0
T1 537500 537499 0 0
T4 16059 16058 0 0
T5 56447 56446 0 0
T6 3510 3509 0 0
T7 6596 6595 0 0
T25 2270 2269 0 0
T26 4285 4284 0 0
T27 1659 1658 0 0
T28 1628 1627 0 0
T29 16556 16555 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T7,T4
01CoveredT6,T7,T4
10CoveredT7,T26,T1 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T7,T4
10CoveredT7,T26,T1
11CoveredT7,T26,T1 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT7,T26,T1
10CoveredT6,T7,T4
11CoveredT6,T7,T4
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 289255239 289254434 0 0
selKnown1 580558299 580557494 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 289255239 289254434 0 0
T1 268485 268484 0 0
T4 5596 5595 0 0
T5 14771 14770 0 0
T6 1708 1707 0 0
T7 3244 3243 0 0
T25 1089 1088 0 0
T26 2075 2074 0 0
T27 811 810 0 0
T28 747 746 0 0
T29 8245 8244 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 580558299 580557494 0 0
T1 537500 537499 0 0
T4 16059 16058 0 0
T5 56447 56446 0 0
T6 3510 3509 0 0
T7 6596 6595 0 0
T25 2270 2269 0 0
T26 4285 4284 0 0
T27 1659 1658 0 0
T28 1628 1627 0 0
T29 16556 16555 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T7,T4
01CoveredT6,T7,T4
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T7,T4
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T7,T4
11CoveredT6,T7,T4
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 144798563 144797758 0 0
selKnown1 580558299 580557494 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 144798563 144797758 0 0
T1 134516 134515 0 0
T4 2798 2797 0 0
T5 7384 7383 0 0
T6 854 853 0 0
T7 1760 1759 0 0
T25 544 543 0 0
T26 1098 1097 0 0
T27 405 404 0 0
T28 374 373 0 0
T29 4123 4122 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 580558299 580557494 0 0
T1 537500 537499 0 0
T4 16059 16058 0 0
T5 56447 56446 0 0
T6 3510 3509 0 0
T7 6596 6595 0 0
T25 2270 2269 0 0
T26 4285 4284 0 0
T27 1659 1658 0 0
T28 1628 1627 0 0
T29 16556 16555 0 0

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