Module Definition
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Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_byp_req

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_byp_req

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6854433 6842590 0 0
T4 182976 40677 0 0
T5 750569 64396 0 0
T6 44779 42716 0 0
T7 78587 77218 0 0
T25 30034 28069 0 0
T26 51767 50085 0 0
T27 23297 21648 0 0
T28 23090 19461 0 0
T29 194919 193786 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 148022690 145716298 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148022690 145716298 0 0
T1 268763 268260 0 0
T4 4014 849 0 0
T5 56447 4522 0 0
T6 1827 1736 0 0
T7 1167 1144 0 0
T25 1560 1449 0 0
T26 1115 1073 0 0
T27 1811 1690 0 0
T28 1680 1399 0 0
T29 2931 2912 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 148022690 145716298 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148022690 145716298 0 0
T1 268763 268260 0 0
T4 4014 849 0 0
T5 56447 4522 0 0
T6 1827 1736 0 0
T7 1167 1144 0 0
T25 1560 1449 0 0
T26 1115 1073 0 0
T27 1811 1690 0 0
T28 1680 1399 0 0
T29 2931 2912 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 148022690 145716298 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 148022690 145716298 0 0
T1 268763 268260 0 0
T4 4014 849 0 0
T5 56447 4522 0 0
T6 1827 1736 0 0
T7 1167 1144 0 0
T25 1560 1449 0 0
T26 1115 1073 0 0
T27 1811 1690 0 0
T28 1680 1399 0 0
T29 2931 2912 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 144798563 144293089 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144798563 144293089 0 0
T1 134516 134394 0 0
T4 2798 847 0 0
T5 7384 1130 0 0
T6 854 833 0 0
T7 1760 1753 0 0
T25 544 527 0 0
T26 1098 1091 0 0
T27 405 384 0 0
T28 374 340 0 0
T29 4123 4112 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 615556861 611279304 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 615556861 611279304 0 0
T1 559914 558859 0 0
T4 16729 3531 0 0
T5 58801 4704 0 0
T6 3656 3473 0 0
T7 6870 6730 0 0
T25 2365 2197 0 0
T26 4464 4295 0 0
T27 1623 1497 0 0
T28 1696 1413 0 0
T29 17246 17135 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 295549172 293491700 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 295549172 293491700 0 0
T1 268763 268260 0 0
T4 8029 1695 0 0
T5 28225 2258 0 0
T6 1755 1668 0 0
T7 3297 3230 0 0
T25 1135 1054 0 0
T26 2143 2062 0 0
T27 783 723 0 0
T28 814 678 0 0
T29 8278 8224 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 580558299 576488187 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 580558299 576488187 0 0
T1 537500 536487 0 0
T4 16059 3389 0 0
T5 56447 4522 0 0
T6 3510 3334 0 0
T7 6596 6461 0 0
T25 2270 2108 0 0
T26 4285 4123 0 0
T27 1659 1538 0 0
T28 1628 1357 0 0
T29 16556 16448 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 289598255 288587202 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 289598255 288587202 0 0
T1 269035 268793 0 0
T4 5596 1694 0 0
T5 14771 2263 0 0
T6 1708 1667 0 0
T7 3520 3506 0 0
T25 1089 1054 0 0
T26 2195 2181 0 0
T27 811 769 0 0
T28 747 678 0 0
T29 8245 8224 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 144798563 144293089 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144798563 144293089 0 0
T1 134516 134394 0 0
T4 2798 847 0 0
T5 7384 1130 0 0
T6 854 833 0 0
T7 1760 1753 0 0
T25 544 527 0 0
T26 1098 1091 0 0
T27 405 384 0 0
T28 374 340 0 0
T29 4123 4112 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 615556861 611279304 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 615556861 611279304 0 0
T1 559914 558859 0 0
T4 16729 3531 0 0
T5 58801 4704 0 0
T6 3656 3473 0 0
T7 6870 6730 0 0
T25 2365 2197 0 0
T26 4464 4295 0 0
T27 1623 1497 0 0
T28 1696 1413 0 0
T29 17246 17135 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 144798563 144293089 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144798563 144293089 0 0
T1 134516 134394 0 0
T4 2798 847 0 0
T5 7384 1130 0 0
T6 854 833 0 0
T7 1760 1753 0 0
T25 544 527 0 0
T26 1098 1091 0 0
T27 405 384 0 0
T28 374 340 0 0
T29 4123 4112 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 144798563 144293089 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144798563 144293089 0 0
T1 134516 134394 0 0
T4 2798 847 0 0
T5 7384 1130 0 0
T6 854 833 0 0
T7 1760 1753 0 0
T25 544 527 0 0
T26 1098 1091 0 0
T27 405 384 0 0
T28 374 340 0 0
T29 4123 4112 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 289598255 288587202 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 289598255 288587202 0 0
T1 269035 268793 0 0
T4 5596 1694 0 0
T5 14771 2263 0 0
T6 1708 1667 0 0
T7 3520 3506 0 0
T25 1089 1054 0 0
T26 2195 2181 0 0
T27 811 769 0 0
T28 747 678 0 0
T29 8245 8224 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 580558299 576488187 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 580558299 576488187 0 0
T1 537500 536487 0 0
T4 16059 3389 0 0
T5 56447 4522 0 0
T6 3510 3334 0 0
T7 6596 6461 0 0
T25 2270 2108 0 0
T26 4285 4123 0 0
T27 1659 1538 0 0
T28 1628 1357 0 0
T29 16556 16448 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 295549172 293491700 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 295549172 293491700 0 0
T1 268763 268260 0 0
T4 8029 1695 0 0
T5 28225 2258 0 0
T6 1755 1668 0 0
T7 3297 3230 0 0
T25 1135 1054 0 0
T26 2143 2062 0 0
T27 783 723 0 0
T28 814 678 0 0
T29 8278 8224 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 615556861 611279304 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 615556861 611279304 0 0
T1 559914 558859 0 0
T4 16729 3531 0 0
T5 58801 4704 0 0
T6 3656 3473 0 0
T7 6870 6730 0 0
T25 2365 2197 0 0
T26 4464 4295 0 0
T27 1623 1497 0 0
T28 1696 1413 0 0
T29 17246 17135 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 615556861 611279304 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 615556861 611279304 0 0
T1 559914 558859 0 0
T4 16729 3531 0 0
T5 58801 4704 0 0
T6 3656 3473 0 0
T7 6870 6730 0 0
T25 2365 2197 0 0
T26 4464 4295 0 0
T27 1623 1497 0 0
T28 1696 1413 0 0
T29 17246 17135 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 615556861 611279304 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 615556861 611279304 0 0
T1 559914 558859 0 0
T4 16729 3531 0 0
T5 58801 4704 0 0
T6 3656 3473 0 0
T7 6870 6730 0 0
T25 2365 2197 0 0
T26 4464 4295 0 0
T27 1623 1497 0 0
T28 1696 1413 0 0
T29 17246 17135 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 615556861 611279304 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 615556861 611279304 0 0
T1 559914 558859 0 0
T4 16729 3531 0 0
T5 58801 4704 0 0
T6 3656 3473 0 0
T7 6870 6730 0 0
T25 2365 2197 0 0
T26 4464 4295 0 0
T27 1623 1497 0 0
T28 1696 1413 0 0
T29 17246 17135 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%