Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	148022690	22724277	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	22724277	0	60
T1	268763	48128	0	0
T2	134272	42935	0	0
T3	25588	3617	0	1
T11	0	12072	0	0
T12	0	32475	0	0
T13	0	12350	0	0
T14	0	33900	0	0
T15	0	3185	0	1
T16	0	7649	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	792	0	1
T21	2353	0	0	0
T22	2294	0	0	0
T23	1385	0	0	0
T24	46925	0	0	0
T38	0	0	0	1
T114	0	0	0	1
T115	0	0	0	1
T116	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1
T119	0	0	0	1