Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	148969735	4680322	0	0
clk_enables_rd_A	148969735	49826	0	0
clk_hints_rd_A	148969735	44214	0	0
extclk_ctrl_rd_A	148969735	55157	0	0
extclk_ctrl_regwen_rd_A	148969735	43423	0	0
jitter_enable_rd_A	148969735	63748	0	0
jitter_regwen_rd_A	148969735	47184	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148969735	4680322	0	0
T2	134272	41337	0	0
T3	25588	0	0	0
T11	617300	0	0	0
T12	0	41689	0	0
T14	0	60348	0	0
T17	0	80740	0	0
T22	2294	0	0	0
T23	1385	0	0	0
T24	46925	0	0	0
T30	0	87807	0	0
T31	19479	0	0	0
T32	11278	0	0	0
T33	0	125378	0	0
T35	1314	0	0	0
T39	0	116865	0	0
T67	0	165448	0	0
T68	0	201929	0	0
T69	0	78179	0	0
T70	1989	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148969735	49826	0	0
T1	268763	0	0	0
T4	4014	0	0	0
T5	56447	0	0	0
T6	1827	3	0	0
T7	1167	0	0	0
T17	0	1609	0	0
T25	1560	0	0	0
T26	1115	0	0	0
T27	1811	0	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T39	0	2189	0	0
T69	0	1642	0	0
T75	0	12	0	0
T116	0	10	0	0
T137	0	4	0	0
T138	0	10	0	0
T139	0	7	0	0
T140	0	3	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148969735	44214	0	0
T1	268763	0	0	0
T4	4014	0	0	0
T5	56447	0	0	0
T6	1827	2	0	0
T7	1167	0	0	0
T17	0	1414	0	0
T25	1560	0	0	0
T26	1115	0	0	0
T27	1811	0	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T38	0	1	0	0
T39	0	2118	0	0
T69	0	1172	0	0
T70	0	4	0	0
T75	0	6	0	0
T116	0	13	0	0
T139	0	1	0	0
T141	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148969735	55157	0	0
T3	25588	0	0	0
T11	617300	0	0	0
T22	2294	50	0	0
T23	1385	0	0	0
T24	46925	0	0	0
T31	19479	46	0	0
T32	11278	0	0	0
T35	1314	0	0	0
T70	1989	0	0	0
T86	0	32	0	0
T111	0	55	0	0
T112	0	67	0	0
T142	0	32	0	0
T143	0	8	0	0
T144	0	21	0	0
T145	0	27	0	0
T146	0	10	0	0
T147	1010	0	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148969735	43423	0	0
T12	121423	0	0	0
T17	0	1450	0	0
T31	19479	20	0	0
T32	11278	0	0	0
T34	62059	0	0	0
T39	0	2143	0	0
T40	0	2645	0	0
T41	1557	0	0	0
T69	0	1330	0	0
T108	0	15	0	0
T110	0	46	0	0
T147	1010	0	0	0
T148	0	11	0	0
T149	0	2735	0	0
T150	0	2555	0	0
T151	2118	0	0	0
T152	1425	0	0	0
T153	2992	0	0	0
T154	3230	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148969735	63748	0	0
T1	268763	0	0	0
T4	4014	0	0	0
T5	56447	0	0	0
T6	1827	105	0	0
T7	1167	0	0	0
T17	0	1891	0	0
T25	1560	0	0	0
T26	1115	0	0	0
T27	1811	0	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T38	0	63	0	0
T70	0	109	0	0
T75	0	512	0	0
T137	0	123	0	0
T138	0	48	0	0
T139	0	108	0	0
T140	0	86	0	0
T141	0	72	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148969735	47184	0	0
T17	255216	1555	0	0
T39	0	2413	0	0
T40	0	2623	0	0
T69	0	1533	0	0
T74	97024	0	0	0
T89	1142	0	0	0
T138	1655	0	0	0
T148	24260	0	0	0
T149	0	3235	0	0
T150	0	2851	0	0
T155	0	1200	0	0
T156	0	4013	0	0
T157	0	1931	0	0
T158	0	2045	0	0
T159	1572	0	0	0
T160	2524	0	0	0
T161	1129	0	0	0
T162	2243	0	0	0
T163	2421	0	0	0