SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T25,T26 |
1 | 0 | Covered | T7,T26,T1 |
1 | 1 | Covered | T7,T26,T1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 580558750 | 4115 | 0 | 0 |
g_div2.Div2Whole_A | 580558750 | 4797 | 0 | 0 |
g_div4.Div4Stepped_A | 289598645 | 4030 | 0 | 0 |
g_div4.Div4Whole_A | 289598645 | 4591 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 580558750 | 4115 | 0 | 0 |
T1 | 537500 | 20 | 0 | 0 |
T2 | 0 | 19 | 0 | 0 |
T4 | 16060 | 0 | 0 | 0 |
T5 | 56448 | 0 | 0 | 0 |
T7 | 6596 | 6 | 0 | 0 |
T11 | 0 | 13 | 0 | 0 |
T12 | 0 | 40 | 0 | 0 |
T13 | 0 | 8 | 0 | 0 |
T18 | 7211 | 0 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 2271 | 0 | 0 | 0 |
T26 | 4286 | 3 | 0 | 0 |
T27 | 1660 | 0 | 0 | 0 |
T28 | 1628 | 0 | 0 | 0 |
T29 | 16557 | 0 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T113 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 580558750 | 4797 | 0 | 0 |
T1 | 537500 | 25 | 0 | 0 |
T2 | 0 | 21 | 0 | 0 |
T4 | 16060 | 0 | 0 | 0 |
T5 | 56448 | 0 | 0 | 0 |
T7 | 6596 | 6 | 0 | 0 |
T11 | 0 | 17 | 0 | 0 |
T12 | 0 | 45 | 0 | 0 |
T13 | 0 | 15 | 0 | 0 |
T18 | 7211 | 0 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 2271 | 0 | 0 | 0 |
T26 | 4286 | 4 | 0 | 0 |
T27 | 1660 | 0 | 0 | 0 |
T28 | 1628 | 0 | 0 | 0 |
T29 | 16557 | 0 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T113 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 289598645 | 4030 | 0 | 0 |
T1 | 269036 | 20 | 0 | 0 |
T2 | 0 | 18 | 0 | 0 |
T4 | 5597 | 0 | 0 | 0 |
T5 | 14771 | 0 | 0 | 0 |
T7 | 3521 | 4 | 0 | 0 |
T11 | 0 | 13 | 0 | 0 |
T12 | 0 | 39 | 0 | 0 |
T13 | 0 | 8 | 0 | 0 |
T18 | 3586 | 0 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 1089 | 0 | 0 | 0 |
T26 | 2196 | 3 | 0 | 0 |
T27 | 811 | 0 | 0 | 0 |
T28 | 748 | 0 | 0 | 0 |
T29 | 8246 | 0 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T113 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 289598645 | 4591 | 0 | 0 |
T1 | 269036 | 24 | 0 | 0 |
T2 | 0 | 18 | 0 | 0 |
T4 | 5597 | 0 | 0 | 0 |
T5 | 14771 | 0 | 0 | 0 |
T7 | 3521 | 6 | 0 | 0 |
T11 | 0 | 15 | 0 | 0 |
T12 | 0 | 45 | 0 | 0 |
T13 | 0 | 15 | 0 | 0 |
T18 | 3586 | 0 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 1089 | 0 | 0 | 0 |
T26 | 2196 | 4 | 0 | 0 |
T27 | 811 | 0 | 0 | 0 |
T28 | 748 | 0 | 0 | 0 |
T29 | 8246 | 0 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T113 | 0 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T25,T26 |
1 | 0 | Covered | T7,T26,T1 |
1 | 1 | Covered | T7,T26,T1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 580558750 | 4115 | 0 | 0 |
g_div2.Div2Whole_A | 580558750 | 4797 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 580558750 | 4115 | 0 | 0 |
T1 | 537500 | 20 | 0 | 0 |
T2 | 0 | 19 | 0 | 0 |
T4 | 16060 | 0 | 0 | 0 |
T5 | 56448 | 0 | 0 | 0 |
T7 | 6596 | 6 | 0 | 0 |
T11 | 0 | 13 | 0 | 0 |
T12 | 0 | 40 | 0 | 0 |
T13 | 0 | 8 | 0 | 0 |
T18 | 7211 | 0 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 2271 | 0 | 0 | 0 |
T26 | 4286 | 3 | 0 | 0 |
T27 | 1660 | 0 | 0 | 0 |
T28 | 1628 | 0 | 0 | 0 |
T29 | 16557 | 0 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T113 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 580558750 | 4797 | 0 | 0 |
T1 | 537500 | 25 | 0 | 0 |
T2 | 0 | 21 | 0 | 0 |
T4 | 16060 | 0 | 0 | 0 |
T5 | 56448 | 0 | 0 | 0 |
T7 | 6596 | 6 | 0 | 0 |
T11 | 0 | 17 | 0 | 0 |
T12 | 0 | 45 | 0 | 0 |
T13 | 0 | 15 | 0 | 0 |
T18 | 7211 | 0 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 2271 | 0 | 0 | 0 |
T26 | 4286 | 4 | 0 | 0 |
T27 | 1660 | 0 | 0 | 0 |
T28 | 1628 | 0 | 0 | 0 |
T29 | 16557 | 0 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T113 | 0 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T25,T26 |
1 | 0 | Covered | T7,T26,T1 |
1 | 1 | Covered | T7,T26,T1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 289598645 | 4030 | 0 | 0 |
g_div4.Div4Whole_A | 289598645 | 4591 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 289598645 | 4030 | 0 | 0 |
T1 | 269036 | 20 | 0 | 0 |
T2 | 0 | 18 | 0 | 0 |
T4 | 5597 | 0 | 0 | 0 |
T5 | 14771 | 0 | 0 | 0 |
T7 | 3521 | 4 | 0 | 0 |
T11 | 0 | 13 | 0 | 0 |
T12 | 0 | 39 | 0 | 0 |
T13 | 0 | 8 | 0 | 0 |
T18 | 3586 | 0 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 1089 | 0 | 0 | 0 |
T26 | 2196 | 3 | 0 | 0 |
T27 | 811 | 0 | 0 | 0 |
T28 | 748 | 0 | 0 | 0 |
T29 | 8246 | 0 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T113 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 289598645 | 4591 | 0 | 0 |
T1 | 269036 | 24 | 0 | 0 |
T2 | 0 | 18 | 0 | 0 |
T4 | 5597 | 0 | 0 | 0 |
T5 | 14771 | 0 | 0 | 0 |
T7 | 3521 | 6 | 0 | 0 |
T11 | 0 | 15 | 0 | 0 |
T12 | 0 | 45 | 0 | 0 |
T13 | 0 | 15 | 0 | 0 |
T18 | 3586 | 0 | 0 | 0 |
T22 | 0 | 10 | 0 | 0 |
T25 | 1089 | 0 | 0 | 0 |
T26 | 2196 | 4 | 0 | 0 |
T27 | 811 | 0 | 0 | 0 |
T28 | 748 | 0 | 0 | 0 |
T29 | 8246 | 0 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T113 | 0 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |