Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	444068070	395	0	0
StatusRise_A	444068070	395	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444068070	395	0	0
T1	806289	0	0	0
T2	402816	0	0	0
T5	169341	0	0	0
T18	11043	0	0	0
T19	8109	0	0	0
T20	47457	0	0	0
T21	7059	0	0	0
T27	5433	16	0	0
T28	5040	0	0	0
T29	8793	0	0	0
T41	0	4	0	0
T42	0	10	0	0
T159	0	16	0	0
T164	0	13	0	0
T165	0	4	0	0
T166	0	13	0	0
T167	0	6	0	0
T168	0	13	0	0
T169	0	14	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444068070	395	0	0
T1	806289	0	0	0
T2	402816	0	0	0
T5	169341	0	0	0
T18	11043	0	0	0
T19	8109	0	0	0
T20	47457	0	0	0
T21	7059	0	0	0
T27	5433	16	0	0
T28	5040	0	0	0
T29	8793	0	0	0
T41	0	4	0	0
T42	0	10	0	0
T159	0	16	0	0
T164	0	13	0	0
T165	0	4	0	0
T166	0	13	0	0
T167	0	6	0	0
T168	0	13	0	0
T169	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	148022690	135	0	0
StatusRise_A	148022690	135	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	135	0	0
T1	268763	0	0	0
T2	134272	0	0	0
T5	56447	0	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T27	1811	6	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	6	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	3	0	0
T169	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	135	0	0
T1	268763	0	0	0
T2	134272	0	0	0
T5	56447	0	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T27	1811	6	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	6	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	3	0	0
T169	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	148022690	120	0	0
StatusRise_A	148022690	120	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	120	0	0
T1	268763	0	0	0
T2	134272	0	0	0
T5	56447	0	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T27	1811	5	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0
T169	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	120	0	0
T1	268763	0	0	0
T2	134272	0	0	0
T5	56447	0	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T27	1811	5	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0
T169	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	148022690	140	0	0
StatusRise_A	148022690	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	140	0	0
T1	268763	0	0	0
T2	134272	0	0	0
T5	56447	0	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T27	1811	5	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T159	0	6	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	5	0	0
T169	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148022690	140	0	0
T1	268763	0	0	0
T2	134272	0	0	0
T5	56447	0	0	0
T18	3681	0	0	0
T19	2703	0	0	0
T20	15819	0	0	0
T21	2353	0	0	0
T27	1811	5	0	0
T28	1680	0	0	0
T29	2931	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T159	0	6	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	5	0	0
T169	0	5	0	0