Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50255	0	0
CgEnOn_A	2147483647	40912	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50255	0	0
T1	6048144	108	0	0
T2	2566185	0	0	0
T4	99398	9	0	0
T5	581228	27	0	0
T6	22451	7	0	0
T7	42653	3	0	0
T18	34802	6	0	0
T19	46271	6	0	0
T20	209655	0	0	0
T21	11222	0	0	0
T25	14498	32	0	0
T26	27577	3	0	0
T27	17864	49	0	0
T28	18050	6	0	0
T29	186126	12	0	0
T30	0	5	0	0
T41	0	5	0	0
T42	0	15	0	0
T159	0	25	0	0
T164	0	20	0	0
T165	0	5	0	0
T166	0	20	0	0
T167	0	10	0	0
T168	0	25	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40912	0	0
T1	6048144	90	0	0
T2	2566185	165	0	0
T4	99398	0	0	0
T5	581228	0	0	0
T6	22451	4	0	0
T7	42653	0	0	0
T11	0	47	0	0
T18	34802	0	0	0
T19	46271	0	0	0
T20	209655	0	0	0
T21	11222	0	0	0
T23	0	15	0	0
T25	14498	29	0	0
T26	27577	0	0	0
T27	17864	46	0	0
T28	18050	3	0	0
T29	186126	9	0	0
T30	0	4	0	0
T41	0	6	0	0
T42	0	15	0	0
T70	0	3	0	0
T147	0	37	0	0
T159	0	25	0	0
T164	0	20	0	0
T165	0	5	0	0
T166	0	20	0	0
T167	0	10	0	0
T168	0	25	0	0
T169	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	289598255	129	0	0
CgEnOn_A	289598255	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289598255	129	0	0
T1	269035	0	0	0
T2	618508	0	0	0
T5	14771	0	0	0
T18	3586	0	0	0
T19	4737	0	0	0
T20	21674	0	0	0
T21	1152	0	0	0
T27	811	5	0	0
T28	747	0	0	0
T29	8245	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289598255	129	0	0
T1	269035	0	0	0
T2	618508	0	0	0
T5	14771	0	0	0
T18	3586	0	0	0
T19	4737	0	0	0
T20	21674	0	0	0
T21	1152	0	0	0
T27	811	5	0	0
T28	747	0	0	0
T29	8245	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	144798563	129	0	0
CgEnOn_A	144798563	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798563	129	0	0
T1	134516	0	0	0
T2	309249	0	0	0
T5	7384	0	0	0
T18	1793	0	0	0
T19	2368	0	0	0
T20	10837	0	0	0
T21	576	0	0	0
T27	405	5	0	0
T28	374	0	0	0
T29	4123	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798563	129	0	0
T1	134516	0	0	0
T2	309249	0	0	0
T5	7384	0	0	0
T18	1793	0	0	0
T19	2368	0	0	0
T20	10837	0	0	0
T21	576	0	0	0
T27	405	5	0	0
T28	374	0	0	0
T29	4123	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	144798563	129	0	0
CgEnOn_A	144798563	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798563	129	0	0
T1	134516	0	0	0
T2	309249	0	0	0
T5	7384	0	0	0
T18	1793	0	0	0
T19	2368	0	0	0
T20	10837	0	0	0
T21	576	0	0	0
T27	405	5	0	0
T28	374	0	0	0
T29	4123	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798563	129	0	0
T1	134516	0	0	0
T2	309249	0	0	0
T5	7384	0	0	0
T18	1793	0	0	0
T19	2368	0	0	0
T20	10837	0	0	0
T21	576	0	0	0
T27	405	5	0	0
T28	374	0	0	0
T29	4123	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	144798563	129	0	0
CgEnOn_A	144798563	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798563	129	0	0
T1	134516	0	0	0
T2	309249	0	0	0
T5	7384	0	0	0
T18	1793	0	0	0
T19	2368	0	0	0
T20	10837	0	0	0
T21	576	0	0	0
T27	405	5	0	0
T28	374	0	0	0
T29	4123	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798563	129	0	0
T1	134516	0	0	0
T2	309249	0	0	0
T5	7384	0	0	0
T18	1793	0	0	0
T19	2368	0	0	0
T20	10837	0	0	0
T21	576	0	0	0
T27	405	5	0	0
T28	374	0	0	0
T29	4123	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	580558299	129	0	0
CgEnOn_A	580558299	122	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580558299	129	0	0
T1	537500	0	0	0
T2	124146	0	0	0
T5	56447	0	0	0
T18	7210	0	0	0
T19	9608	0	0	0
T20	43386	0	0	0
T21	2328	0	0	0
T27	1659	5	0	0
T28	1628	0	0	0
T29	16556	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580558299	122	0	0
T1	537500	0	0	0
T2	124146	0	0	0
T5	56447	0	0	0
T18	7210	0	0	0
T19	9608	0	0	0
T20	43386	0	0	0
T21	2328	0	0	0
T27	1659	5	0	0
T28	1628	0	0	0
T29	16556	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0
T168	0	5	0	0
T169	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	615556861	139	0	0
CgEnOn_A	615556861	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	139	0	0
T1	559914	0	0	0
T2	134272	0	0	0
T5	58801	0	0	0
T18	7511	0	0	0
T19	10009	0	0	0
T20	45195	0	0	0
T21	2425	0	0	0
T27	1623	6	0	0
T28	1696	0	0	0
T29	17246	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	6	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	3	0	0
T169	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	135	0	0
T1	559914	0	0	0
T2	134272	0	0	0
T5	58801	0	0	0
T18	7511	0	0	0
T19	10009	0	0	0
T20	45195	0	0	0
T21	2425	0	0	0
T27	1623	6	0	0
T28	1696	0	0	0
T29	17246	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	6	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	3	0	0
T169	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	615556861	139	0	0
CgEnOn_A	615556861	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	139	0	0
T1	559914	0	0	0
T2	134272	0	0	0
T5	58801	0	0	0
T18	7511	0	0	0
T19	10009	0	0	0
T20	45195	0	0	0
T21	2425	0	0	0
T27	1623	6	0	0
T28	1696	0	0	0
T29	17246	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	6	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	3	0	0
T169	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	135	0	0
T1	559914	0	0	0
T2	134272	0	0	0
T5	58801	0	0	0
T18	7511	0	0	0
T19	10009	0	0	0
T20	45195	0	0	0
T21	2425	0	0	0
T27	1623	6	0	0
T28	1696	0	0	0
T29	17246	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T159	0	5	0	0
T164	0	6	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	0	2	0	0
T168	0	3	0	0
T169	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	295549172	142	0	0
CgEnOn_A	295549172	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295549172	142	0	0
T1	268763	0	0	0
T2	627240	0	0	0
T5	28225	0	0	0
T18	3605	0	0	0
T19	4804	0	0	0
T20	21694	0	0	0
T21	1164	0	0	0
T27	783	5	0	0
T28	814	0	0	0
T29	8278	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T159	0	6	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	5	0	0
T169	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295549172	141	0	0
T1	268763	0	0	0
T2	627240	0	0	0
T5	28225	0	0	0
T18	3605	0	0	0
T19	4804	0	0	0
T20	21694	0	0	0
T21	1164	0	0	0
T27	783	5	0	0
T28	814	0	0	0
T29	8278	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T159	0	6	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	2	0	0
T168	0	5	0	0
T169	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T41,T42
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	144798563	7840	0	0
CgEnOn_A	144798563	5516	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798563	7840	0	0
T1	134516	25	0	0
T4	2798	3	0	0
T5	7384	9	0	0
T6	854	2	0	0
T7	1760	1	0	0
T25	544	12	0	0
T26	1098	1	0	0
T27	405	6	0	0
T28	374	1	0	0
T29	4123	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144798563	5516	0	0
T1	134516	19	0	0
T2	0	40	0	0
T4	2798	0	0	0
T5	7384	0	0	0
T6	854	1	0	0
T7	1760	0	0	0
T11	0	7	0	0
T23	0	6	0	0
T25	544	11	0	0
T26	1098	0	0	0
T27	405	5	0	0
T28	374	0	0	0
T29	4123	0	0	0
T41	0	1	0	0
T70	0	1	0	0
T147	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T41,T42
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	289598255	7935	0	0
CgEnOn_A	289598255	5611	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289598255	7935	0	0
T1	269035	26	0	0
T4	5596	3	0	0
T5	14771	9	0	0
T6	1708	2	0	0
T7	3520	1	0	0
T25	1089	11	0	0
T26	2195	1	0	0
T27	811	6	0	0
T28	747	2	0	0
T29	8245	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289598255	5611	0	0
T1	269035	20	0	0
T2	0	39	0	0
T4	5596	0	0	0
T5	14771	0	0	0
T6	1708	1	0	0
T7	3520	0	0	0
T11	0	10	0	0
T23	0	4	0	0
T25	1089	10	0	0
T26	2195	0	0	0
T27	811	5	0	0
T28	747	1	0	0
T29	8245	0	0	0
T70	0	1	0	0
T147	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T41,T42
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	580558299	7951	0	0
CgEnOn_A	580558299	5620	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580558299	7951	0	0
T1	537500	28	0	0
T4	16059	3	0	0
T5	56447	9	0	0
T6	3510	2	0	0
T7	6596	1	0	0
T25	2270	9	0	0
T26	4285	1	0	0
T27	1659	6	0	0
T28	1628	2	0	0
T29	16556	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580558299	5620	0	0
T1	537500	22	0	0
T2	0	43	0	0
T4	16059	0	0	0
T5	56447	0	0	0
T6	3510	1	0	0
T7	6596	0	0	0
T11	0	9	0	0
T23	0	5	0	0
T25	2270	8	0	0
T26	4285	0	0	0
T27	1659	5	0	0
T28	1628	1	0	0
T29	16556	0	0	0
T70	0	1	0	0
T147	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T41,T42
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	295549172	7915	0	0
CgEnOn_A	295549172	5583	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295549172	7915	0	0
T1	268763	24	0	0
T4	8029	3	0	0
T5	28225	9	0	0
T6	1755	2	0	0
T7	3297	1	0	0
T25	1135	12	0	0
T26	2143	1	0	0
T27	783	6	0	0
T28	814	2	0	0
T29	8278	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	295549172	5583	0	0
T1	268763	18	0	0
T2	0	40	0	0
T4	8029	0	0	0
T5	28225	0	0	0
T6	1755	1	0	0
T7	3297	0	0	0
T11	0	9	0	0
T23	0	5	0	0
T25	1135	11	0	0
T26	2143	0	0	0
T27	783	5	0	0
T28	814	1	0	0
T29	8278	0	0	0
T70	0	1	0	0
T147	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	615556861	4382	0	0
CgEnOn_A	615556861	4378	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	4382	0	0
T1	559914	29	0	0
T2	0	43	0	0
T4	16729	0	0	0
T5	58801	0	0	0
T6	3656	1	0	0
T7	6870	0	0	0
T11	0	21	0	0
T18	0	6	0	0
T19	0	6	0	0
T21	0	5	0	0
T25	2365	0	0	0
T26	4464	0	0	0
T27	1623	6	0	0
T28	1696	1	0	0
T29	17246	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	4378	0	0
T1	559914	29	0	0
T2	0	43	0	0
T4	16729	0	0	0
T5	58801	0	0	0
T6	3656	1	0	0
T7	6870	0	0	0
T11	0	21	0	0
T18	0	6	0	0
T19	0	6	0	0
T21	0	5	0	0
T25	2365	0	0	0
T26	4464	0	0	0
T27	1623	6	0	0
T28	1696	1	0	0
T29	17246	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	615556861	4394	0	0
CgEnOn_A	615556861	4390	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	4394	0	0
T1	559914	21	0	0
T2	0	38	0	0
T4	16729	0	0	0
T5	58801	0	0	0
T6	3656	1	0	0
T7	6870	0	0	0
T11	0	18	0	0
T18	0	10	0	0
T19	0	7	0	0
T21	0	6	0	0
T25	2365	0	0	0
T26	4464	0	0	0
T27	1623	6	0	0
T28	1696	1	0	0
T29	17246	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	4390	0	0
T1	559914	21	0	0
T2	0	38	0	0
T4	16729	0	0	0
T5	58801	0	0	0
T6	3656	1	0	0
T7	6870	0	0	0
T11	0	18	0	0
T18	0	10	0	0
T19	0	7	0	0
T21	0	6	0	0
T25	2365	0	0	0
T26	4464	0	0	0
T27	1623	6	0	0
T28	1696	1	0	0
T29	17246	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	615556861	4391	0	0
CgEnOn_A	615556861	4387	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	4391	0	0
T1	559914	26	0	0
T2	0	27	0	0
T4	16729	0	0	0
T5	58801	0	0	0
T6	3656	1	0	0
T7	6870	0	0	0
T11	0	19	0	0
T18	0	9	0	0
T19	0	9	0	0
T21	0	8	0	0
T25	2365	0	0	0
T26	4464	0	0	0
T27	1623	6	0	0
T28	1696	1	0	0
T29	17246	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	4387	0	0
T1	559914	26	0	0
T2	0	27	0	0
T4	16729	0	0	0
T5	58801	0	0	0
T6	3656	1	0	0
T7	6870	0	0	0
T11	0	19	0	0
T18	0	9	0	0
T19	0	9	0	0
T21	0	8	0	0
T25	2365	0	0	0
T26	4464	0	0	0
T27	1623	6	0	0
T28	1696	1	0	0
T29	17246	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T5
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	615556861	4382	0	0
CgEnOn_A	615556861	4378	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	4382	0	0
T1	559914	25	0	0
T2	0	28	0	0
T4	16729	0	0	0
T5	58801	0	0	0
T6	3656	1	0	0
T7	6870	0	0	0
T11	0	24	0	0
T18	0	7	0	0
T19	0	8	0	0
T21	0	8	0	0
T25	2365	0	0	0
T26	4464	0	0	0
T27	1623	6	0	0
T28	1696	1	0	0
T29	17246	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615556861	4378	0	0
T1	559914	25	0	0
T2	0	28	0	0
T4	16729	0	0	0
T5	58801	0	0	0
T6	3656	1	0	0
T7	6870	0	0	0
T11	0	24	0	0
T18	0	7	0	0
T19	0	8	0	0
T21	0	8	0	0
T25	2365	0	0	0
T26	4464	0	0	0
T27	1623	6	0	0
T28	1696	1	0	0
T29	17246	7	0	0