Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	652122	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3884363

1

T6

18

T1

45636

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1113632	1			T6	17		T1	12408		T7	1
values[0x0]	1571907	1			T6	17		T1	18032		T7	1
values[0x1]	1850946	1			T6	18		T1	21374		T7	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	355927	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4180558

1

T6

24

T1

48762

T7

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19338	1			T1	189		T2	43		T3	552
valid_sources[0x01]	19453	1			T1	200		T18	1		T70	17
valid_sources[0x02]	17974	1			T1	196		T43	3		T2	263
valid_sources[0x03]	18064	1			T1	211		T43	1		T28	1
valid_sources[0x04]	17278	1			T6	1		T1	200		T87	1
valid_sources[0x05]	17161	1			T1	174		T87	1		T2	427
valid_sources[0x06]	17533	1			T1	228		T28	4		T2	377
valid_sources[0x07]	17458	1			T1	198		T18	2		T43	1
valid_sources[0x08]	16739	1			T1	174		T4	6		T17	1
valid_sources[0x09]	18833	1			T1	183		T28	2		T2	16
valid_sources[0x0a]	16900	1			T1	194		T18	1		T22	1
valid_sources[0x0b]	19954	1			T1	208		T18	1		T5	287
valid_sources[0x0c]	16883	1			T1	193		T18	1		T28	2
valid_sources[0x0d]	18557	1			T6	1		T1	204		T18	2
valid_sources[0x0e]	18093	1			T6	1		T1	215		T43	1
valid_sources[0x0f]	17473	1			T1	202		T23	1		T2	157
valid_sources[0x10]	18685	1			T1	207		T17	2		T28	1
valid_sources[0x11]	18173	1			T1	193		T28	2		T2	158
valid_sources[0x12]	17103	1			T1	210		T18	1		T28	2
valid_sources[0x13]	17214	1			T1	251		T28	5		T2	272
valid_sources[0x14]	17481	1			T1	212		T18	1		T2	144
valid_sources[0x15]	17970	1			T1	186		T28	1		T2	155
valid_sources[0x16]	18126	1			T1	205		T2	164		T3	521
valid_sources[0x17]	18372	1			T1	186		T2	365		T3	514
valid_sources[0x18]	18665	1			T1	201		T22	2		T28	2
valid_sources[0x19]	16511	1			T1	217		T17	1		T18	1
valid_sources[0x1a]	17958	1			T1	178		T18	1		T43	1
valid_sources[0x1b]	17341	1			T1	174		T23	1		T43	1
valid_sources[0x1c]	16849	1			T1	196		T17	1		T18	2
valid_sources[0x1d]	18306	1			T1	180		T7	4		T17	1
valid_sources[0x1e]	18904	1			T1	194		T17	1		T18	1
valid_sources[0x1f]	17148	1			T6	1		T1	196		T87	4
valid_sources[0x20]	17030	1			T6	2		T1	202		T28	4
valid_sources[0x21]	16654	1			T1	191		T18	1		T22	1
valid_sources[0x22]	17467	1			T1	202		T2	183		T3	538
valid_sources[0x23]	18082	1			T1	201		T28	1		T2	225
valid_sources[0x24]	18267	1			T1	232		T28	1		T2	93
valid_sources[0x25]	17317	1			T6	1		T1	208		T18	1
valid_sources[0x26]	16312	1			T1	199		T18	2		T43	1
valid_sources[0x27]	17872	1			T1	195		T4	13		T17	1
valid_sources[0x28]	17188	1			T1	195		T23	1		T28	1
valid_sources[0x29]	18630	1			T1	201		T43	3		T28	6
valid_sources[0x2a]	18865	1			T1	190		T17	1		T28	1
valid_sources[0x2b]	18398	1			T1	219		T23	1		T2	327
valid_sources[0x2c]	20211	1			T1	232		T18	1		T28	1
valid_sources[0x2d]	18533	1			T1	213		T18	2		T28	2
valid_sources[0x2e]	17915	1			T1	228		T22	4		T87	2
valid_sources[0x2f]	18599	1			T1	203		T28	1		T2	584
valid_sources[0x30]	18209	1			T1	213		T23	3		T28	1
valid_sources[0x31]	18083	1			T1	206		T43	1		T2	233
valid_sources[0x32]	17811	1			T1	194		T28	2		T2	111
valid_sources[0x33]	17515	1			T1	167		T17	1		T18	1
valid_sources[0x34]	17595	1			T1	194		T18	1		T22	2
valid_sources[0x35]	17493	1			T6	1		T1	229		T17	1
valid_sources[0x36]	16534	1			T1	210		T22	1		T2	228
valid_sources[0x37]	18596	1			T1	168		T70	21		T2	597
valid_sources[0x38]	18079	1			T6	1		T1	201		T28	1
valid_sources[0x39]	17458	1			T6	1		T1	198		T28	1
valid_sources[0x3a]	17491	1			T1	209		T17	1		T43	3
valid_sources[0x3b]	17840	1			T1	184		T4	9		T17	1
valid_sources[0x3c]	17114	1			T1	201		T17	2		T18	1
valid_sources[0x3d]	17141	1			T1	229		T17	1		T43	1
valid_sources[0x3e]	17311	1			T1	200		T18	1		T28	1
valid_sources[0x3f]	17628	1			T1	209		T23	3		T2	166
valid_sources[0x40]	18001	1			T1	218		T4	1		T17	3
valid_sources[0x41]	19040	1			T1	171		T22	1		T43	1
valid_sources[0x42]	18574	1			T1	206		T22	1		T23	2
valid_sources[0x43]	18820	1			T1	202		T21	3		T43	2
valid_sources[0x44]	17929	1			T6	1		T1	192		T17	1
valid_sources[0x45]	17577	1			T1	210		T22	2		T28	2
valid_sources[0x46]	17776	1			T1	235		T22	1		T28	1
valid_sources[0x47]	17408	1			T6	1		T1	222		T17	1
valid_sources[0x48]	17792	1			T1	200		T18	1		T22	1
valid_sources[0x49]	18589	1			T6	3		T1	206		T4	5
valid_sources[0x4a]	18792	1			T1	208		T18	1		T72	3
valid_sources[0x4b]	18056	1			T1	196		T70	9		T87	3
valid_sources[0x4c]	17139	1			T1	187		T17	1		T87	1
valid_sources[0x4d]	16221	1			T1	193		T18	2		T28	1
valid_sources[0x4e]	18074	1			T1	209		T28	2		T2	72
valid_sources[0x4f]	18689	1			T1	208		T17	1		T28	3
valid_sources[0x50]	16523	1			T1	209		T43	2		T71	10
valid_sources[0x51]	18103	1			T6	1		T1	200		T17	1
valid_sources[0x52]	18231	1			T1	200		T21	1		T2	25
valid_sources[0x53]	17953	1			T1	191		T18	1		T22	1
valid_sources[0x54]	18099	1			T1	200		T28	5		T2	127
valid_sources[0x55]	17174	1			T1	200		T17	1		T22	1
valid_sources[0x56]	18401	1			T6	1		T1	220		T28	2
valid_sources[0x57]	17691	1			T1	234		T22	1		T73	1
valid_sources[0x58]	16334	1			T6	1		T1	199		T23	1
valid_sources[0x59]	17228	1			T6	3		T1	177		T18	1
valid_sources[0x5a]	17143	1			T1	209		T28	1		T2	12
valid_sources[0x5b]	18217	1			T1	215		T22	1		T28	1
valid_sources[0x5c]	17437	1			T1	195		T4	2		T22	2
valid_sources[0x5d]	18355	1			T1	224		T2	30		T3	549
valid_sources[0x5e]	19501	1			T1	215		T18	1		T28	6
valid_sources[0x5f]	16793	1			T1	214		T43	2		T2	105
valid_sources[0x60]	17473	1			T1	182		T4	13		T17	1
valid_sources[0x61]	18072	1			T6	1		T1	197		T28	1
valid_sources[0x62]	16971	1			T1	206		T28	4		T2	7
valid_sources[0x63]	17190	1			T1	195		T43	1		T2	118
valid_sources[0x64]	17766	1			T6	3		T1	221		T17	1
valid_sources[0x65]	17797	1			T1	200		T22	1		T23	1
valid_sources[0x66]	17893	1			T1	183		T28	1		T73	1
valid_sources[0x67]	17010	1			T1	206		T2	105		T3	531
valid_sources[0x68]	17962	1			T6	1		T1	210		T17	2
valid_sources[0x69]	17539	1			T1	229		T28	1		T2	6
valid_sources[0x6a]	18646	1			T1	203		T4	9		T2	239
valid_sources[0x6b]	17109	1			T6	1		T1	203		T18	1
valid_sources[0x6c]	19056	1			T6	1		T1	240		T2	355
valid_sources[0x6d]	17034	1			T1	199		T17	1		T22	1
valid_sources[0x6e]	16360	1			T1	201		T22	1		T43	1
valid_sources[0x6f]	17485	1			T1	195		T17	1		T18	1
valid_sources[0x70]	19518	1			T1	229		T18	1		T22	2
valid_sources[0x71]	16250	1			T6	1		T1	196		T43	1
valid_sources[0x72]	18111	1			T1	224		T17	1		T43	1
valid_sources[0x73]	19823	1			T1	190		T23	1		T28	1
valid_sources[0x74]	17710	1			T6	1		T1	181		T17	1
valid_sources[0x75]	17673	1			T1	198		T43	2		T2	13
valid_sources[0x76]	18355	1			T1	184		T4	1		T18	1
valid_sources[0x77]	19276	1			T1	208		T2	124		T3	565
valid_sources[0x78]	19261	1			T1	214		T22	2		T23	2
valid_sources[0x79]	17476	1			T1	217		T18	1		T22	1
valid_sources[0x7a]	18222	1			T1	199		T18	1		T19	55
valid_sources[0x7b]	17695	1			T6	1		T1	196		T18	1
valid_sources[0x7c]	17546	1			T1	198		T43	1		T28	1
valid_sources[0x7d]	18797	1			T1	194		T18	1		T28	1
valid_sources[0x7e]	18633	1			T1	203		T43	1		T2	186
valid_sources[0x7f]	17986	1			T1	194		T22	1		T43	2
valid_sources[0x80]	17455	1			T6	1		T1	212		T87	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

981306

1

T6

10

T1

11430

T4

3

values[0x0]

all_enables

biggest_size

1474938

1

T6

6

T1

17259

T7

1

values[0x1]

all_enables

biggest_size

1428119

1

T6

2

T1

16947

T7

2