Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T43
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T43
1	0	Covered	T40,T41,T42
1	1	Covered	T6,T1,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1177309093	14744	0	0
GateOpen_A	1177309093	21239	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1177309093	14744	0	0
T1	935176	223	0	0
T2	0	133	0	0
T3	0	325	0	0
T4	93216	0	0	0
T7	4066	0	0	0
T17	5562	0	0	0
T18	5550	0	0	0
T19	47858	0	0	0
T20	8085	0	0	0
T21	2857	0	0	0
T22	8154	4	0	0
T23	5517	0	0	0
T40	0	8	0	0
T41	0	12	0	0
T43	0	4	0	0
T78	0	4	0	0
T188	0	22	0	0
T190	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1177309093	21239	0	0
T1	935176	227	0	0
T4	93216	4	0	0
T7	4066	0	0	0
T17	5562	4	0	0
T18	5550	4	0	0
T19	47858	4	0	0
T20	8085	4	0	0
T21	2857	4	0	0
T22	8154	8	0	0
T23	5517	4	0	0
T70	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T43
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T43
1	0	Covered	T40,T41,T42
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	130647178	3508	0	0
GateOpen_A	130647178	5129	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130647178	3508	0	0
T1	516951	53	0	0
T2	0	33	0	0
T3	0	77	0	0
T4	8744	0	0	0
T7	435	0	0	0
T17	659	0	0	0
T18	611	0	0	0
T19	5741	0	0	0
T20	904	0	0	0
T21	300	0	0	0
T22	898	1	0	0
T23	632	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T78	0	1	0	0
T188	0	5	0	0
T190	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130647178	5129	0	0
T1	516951	54	0	0
T4	8744	1	0	0
T7	435	0	0	0
T17	659	1	0	0
T18	611	1	0	0
T19	5741	1	0	0
T20	904	1	0	0
T21	300	1	0	0
T22	898	2	0	0
T23	632	1	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T43
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T43
1	0	Covered	T40,T41,T42
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	261295306	3740	0	0
GateOpen_A	261295306	5361	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261295306	3740	0	0
T1	103391	56	0	0
T2	0	35	0	0
T3	0	88	0	0
T4	17488	0	0	0
T7	869	0	0	0
T17	1321	0	0	0
T18	1221	0	0	0
T19	11482	0	0	0
T20	1808	0	0	0
T21	599	0	0	0
T22	1795	1	0	0
T23	1267	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T78	0	1	0	0
T188	0	5	0	0
T190	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261295306	5361	0	0
T1	103391	57	0	0
T4	17488	1	0	0
T7	869	0	0	0
T17	1321	1	0	0
T18	1221	1	0	0
T19	11482	1	0	0
T20	1808	1	0	0
T21	599	1	0	0
T22	1795	2	0	0
T23	1267	1	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T43
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T43
1	0	Covered	T40,T41,T42
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	520094035	3752	0	0
GateOpen_A	520094035	5378	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520094035	3752	0	0
T1	207582	58	0	0
T2	0	31	0	0
T3	0	78	0	0
T4	35055	0	0	0
T7	1841	0	0	0
T17	2388	0	0	0
T18	2479	0	0	0
T19	20423	0	0	0
T20	3582	0	0	0
T21	1305	0	0	0
T22	3641	1	0	0
T23	2412	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T78	0	1	0	0
T188	0	6	0	0
T190	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520094035	5378	0	0
T1	207582	59	0	0
T4	35055	1	0	0
T7	1841	0	0	0
T17	2388	1	0	0
T18	2479	1	0	0
T19	20423	1	0	0
T20	3582	1	0	0
T21	1305	1	0	0
T22	3641	2	0	0
T23	2412	1	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T43
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T43
1	0	Covered	T40,T41,T42
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	265272574	3744	0	0
GateOpen_A	265272574	5371	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265272574	3744	0	0
T1	107252	56	0	0
T2	0	34	0	0
T3	0	82	0	0
T4	31929	0	0	0
T7	921	0	0	0
T17	1194	0	0	0
T18	1239	0	0	0
T19	10212	0	0	0
T20	1791	0	0	0
T21	653	0	0	0
T22	1820	1	0	0
T23	1206	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T78	0	1	0	0
T188	0	6	0	0
T190	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265272574	5371	0	0
T1	107252	57	0	0
T4	31929	1	0	0
T7	921	0	0	0
T17	1194	1	0	0
T18	1239	1	0	0
T19	10212	1	0	0
T20	1791	1	0	0
T21	653	1	0	0
T22	1820	2	0	0
T23	1206	1	0	0
T70	0	1	0	0